The Core Microarchitecture (Cont.)
Intel Advanced Smart Cache: Unlike Netburst-based, dual-core Pentium D processors that feature a certain amount of distinct L2 cache per processor core, Core microarchitecture based processors, like the Core 2 Duo E6700 and Core 2 Extreme X6800 we'll be evaluating in this article, are equipped with a single, shared cache that can be accessed entirely by either core. With current dual-core processors, each core has to store data in its own L2 cache, and that data cannot be shared between cores. With the Core microarchitecture, however, each execution core has access to the whole L2 cache (4MB or 2MB depending on the model), improving overall efficiency. Intel's Advanced Smart Cache technology also allows each core to dynamically utilize up to 100% of available L2 cache. So, if one core doesn't require large amounts of L2 cache and another does, the second core can increase its allocation of L2 cache on the fly, which will reduce the number of cache misses, and in turn increase performance.
Intel Smart Memory Access: The Smart Memory Access technology employed in the Core microarchitecture, is designed to improve overall system performance by optimizing the use of available memory bandwidth and hiding the latency associated with accessing system memory over the front side bus. Smart Memory Access incorporates a new feature called memory disambiguation that increases the efficiency of out-of-order processing through the use of built-in logic that pre-fetches and loads data for instructions before all previous load instructions are executed. Smart Memory Access uses advanced algorithms to evaluate whether or not a load can be executed ahead of a preceding store. If it can, then the load instructions can be scheduled before the store instructions to enable increased instruction-level parallelism. Intel Smart Memory Access also incorporates new memory pre-fetchers that grab data and store it in the processor's cache before it's specifically requested, so that data can be readily accessed from fast on-die cache when needed. The Core microarchitecture uses two prefetchers per L1 cache and two prefetchers per L2 cache.
Intel Advanced Digital Media Boost: With Intel's previous generation of processors, 128-bit SSE, SSE2, and SSE3 instructions were typically executed at a rate of one complete instruction every two clock-cycles. With the Core microarchitecture based processors that feature Intel's Advanced Digital Media Boost feature though, 128-bit Streaming SIMD Extension (SSE) instructions can typically be completely executed in a single clock cycle, which effectively doubles the speed at which instructions of this type can be executed. Advanced Digital Media Boost will come into play when executing multimedia operations that involve graphics, video and audio that use SSE, SSE2, or SSE3 instructions.
Intel Intelligent Power Capability: As its name implies, Intelligent Power Capability is a set of features designed to reduce overall power consumption. This feature is in control of the power consumption of all of a Core-based processor's execution cores. Intelligent Power Capability incorporates fine-grained logic control that enables individual components within the processor core only when they are needed. In addition to this capability, many arrays within the CPU are split so that data required in some modes of operation can be put into a low-power state when it's not in use. Reductions in power consumption also come by way of enhancements made to Intel's 65nm manufacturing process node, like the use of Low-K dielectrics and strained silicon, and through the use of low-leakage and "sleep" transistors and Enhanced SpeedStep.