VIA's Glenn Henry Speaks On New Low Power Isaiah Processor

VIA's Glenn Henry Speaks On New Low Power Isaiah Processor

With all the buzz around VIA's recent announcement of their next generation low power Isaiah mobile processor and the parade of online coverage of the recent press event VIA held at their Centaur design center in Texas, we felt rather than regurgitating the usual marketing fluff and press pitch material, we would get together with some of VIA's top architecture and design brass in a "fireside chat" sort of venue. The idea was to provide a little more insight into what the team at VIA feels will be the real value proposition of their ultra low power Isaiah mobile X86 processor and how the product will differentiate versus current and future offerings from the likes of Intel, AMD and others.  Our direct line of contact was with VIA's Centaur design center president, Glenn Henry.  Former Dell CTO and IBM Engineering Fellow, Glenn founded Centaur back in 1995 and the highly successful company has the lowest employee attrition rate in the industry - no small feat for a semiconductor design house.

Thanks for taking time out to chat with us today about the new Isaiah CPU architecture, Glenn. 

Q:  With more than triple the number of transistors, a larger die, and potentially higher frequencies, how was Centaur able to lower Isaiah’s TDP (thermal power design) in comparison to your C7 core?  Is the power savings a direct result of using a 65nm manufacturing process, or are there specific design elements within the core that lend themselves to power savings? 

Glenn Henry:  There are many areas in the chip where we optimized the design to improve overall power consumption above and beyond what a 65nm manufacturing process brings.  We worked on the power profile of the chip first and didn’t focus as much on increased clock speed.  We looked at performance-per-watt and made that our priority and then tuned the design for performance.  The new Isaiah CPU will consume only about as much power as our current C7 but offer significant performance increases of up to two times our C7 chip. 

Q:  You’ve stated that Isaiah based processors are likely to outperform Intel’s upcoming Silverthorne processor.  What is it about Isaiah that gives it this perceived advantage?  Is there a higher IPC capability in the design versus Intel’s architecture?  What fundamental blocks of the chip offer you a competitive advantage, in your opinion.

Glenn Henry:  Had I known that I would have gotten so much publicity for that statement, I may not have said it BUT, in a nutshell, we suspect Intel’s Silverthorne is an in-order processor (instruction fetch, operand dispatch, execution, and then function unit/result write).  Isaiah is an out-of-order processor and out of order processors are just, faster.   Isaiah is capable of three X86 instructions per clock and can execute up to 7 micro-instructions per clock with our superscalar architecture.  They’ll (Intel) likely only be able to do 1 or 2 X86 instructions per clock.  We also think our 1MB L2 Cache and dual 64K L1 caches going to be larger than theirs but we can’t confirm this officially obviously.  So the big bullets are; out of order execution, a wider three-issue superscalar architecture and likely larger caches versus the other guy’s (Intel’s) chip – at least from what we think we know of their product at this point in time.


The floating point unit in the Isaiah core seems to be a major contributing factor to its increased performance over C7.  What are the key reasons for its relatively stronger performance?  Do any other aspects of the Isaiah core or the system architecture significantly contribute to its increased relative performance?

Glenn Henry:   Isaiah's FPU performance is a big gain in some applications for sure.   We’re relatively a lot faster on applications that are heavy on FPU but also lot faster than our previous product (C7) on integer operations.  How we achieved greater FPU performance is a patentable invention.  We came up with a new approach to doing floating-point adds and put a lot of detailed engineering work on FP multiplies.  Centaur started working on the FPU architecture on the first day.  It was something we didn’t do as well on the C7 but we made it a top priority on Isaiah and put a lot of focus on FPU performance.

Q: Is VIA / Centaur also developing lower power, higher performing chipsets for the Isaiah architecture to further enhance the entire platform’s power and thermal characteristics?  

Glenn Henry:  Yes, we can’t offer any info on the new chipsets right now but there will likely be a new chipset with the part when it launches.  In addition, Isaiah will be compatible with our current chipsets, which will be a big advantage for our current customers in their migration efforts to Isaiah.

  It is noted that the Isaiah core will have on-board hardware processing engines for security algorithms such as Random Number Generation, AES encryption and SHA secure hashing (your “Padlock” technology).  What sort of line rate can the processor support under these conditions?

Glenn Henry:  We’ve had security processing and secure hashing in our products for a long time but it’s a bit difficult to translate it into CPU resource consumption.    I’ll tell you this; our peak AES encryption throughput is about 20GB/sec, assuming data is available at that rate and that would consume 100% of the CPU resources.  So as you can imagine, a single Gig-E link can be accommodated with full hardware offload in the CPU, with very low overall CPU utilization.  Everything with our encryption and security technology is done totally in hardware, so it’s blindingly fast.

Related content