AMD Beema and Mullins Low Power 2014 APUs Tested
CPU, GPU, Security and IO Enhacements
Beema and Mullins are the first x86 processors to feature an integrated ARM core for security features. But that’s not all they’re about. Though the designs feature the same architectural components as last year’s Kabini, AMD has tweaked a few things to improve performance and power efficiency.
The CPU cores features in Beema and Mullins are architecturally similar to the Jaguar cores used in Kabini, but the new Puma+ cores as AMD is calling them can hit higher clock speeds in lower power envelopes and have 19% lower leakage current too. AMD says the leakage reduction comes by way of a mixture of the chip’s design and manufacturing process. The chips are not made on a new process node, but there were improvements to the tech as the 28nm process has matured.
The GPU cores have been enhanced in a similar manner. The GCN-based graphics engine used in Beema / Mullins run about 100MHz – 200MHz faster than the previous generation, but has been optimized for power efficiency and also offers a 38% reduction in leakage. Again, the leakage reduction is mostly a result of the chip’s design and maturity of its manufacturing process.
AMD didn’t stop at the GPU and GPU cores, however. It has also optimized the memory and display interfaces for higher performance and lower power. The chips support a new low-power DDR-1333 mode, which reportedly offers a 500mW reduction compared to standard DDR3-1333. Conversely, the higher end configurations also support up to DDR3-1866 speeds, for higher bandwidth, and ultimately increased performance. The graphics engines in AMD’s APUs are often starved for memory bandwidth, so the higher max memory speed will increase performance in many workloads considerably.
The display interface has also been enhanced with voltage mode logic that also helps bring power down. With high resolution displays, AMD estimates a 200mW power reduction overall.
Perhaps the biggest change to arrive with Beema and Mullins is the new ARM-based Platform Security Processor, or PSP. The PSP uses the industry standard ARM TrustZone system security framework and is essentially a Cyptographic co-processor with RSA, SHA, ECC, and AES engines. The core also has hardware logic for secure boot, and though it has its own isolated ROM and SRAM, the PSP can assess system memory and other resources.
To leverage the PSP, software must be engineered to support it, but since it uses the existing ARM TrustZone system, support should come rather quickly. The PSP gives Beema and Mullins based ssytems and devices the ability to support a full Trusted Execution Environment (TEE), security-aware applications and secure services, and Trusted Applications (TA).
In addition to improving the power characteristics of Beema and Mullins versus the previous generation, AMD has also enabled a new skin temperature away power management systems, dubbed STAPM, along with more intelligent boost controls. What STAPM does is allow the APU to boost to maximum speeds, for longer periods of time, without resulting in uncomfortable-to-hold temperatures on the skin (or outer shell) of the device. Without STAPM, AMD was leaving performance on the table, but with it, the APUs can churn through workloads faster, without hitting excessive temps, and with overall lower power. When in boost mode, the APU will obviously use more power during peak loads, but because these new APU can hit higher clocks, they can complete tasks faster, which in turn allows unused portions of the platform to be shut down faster as well.