Intel Developer Forum 2010 CEO Keynote Coverage

Following Paul Otellini, David “Dadi” Perlmutter, Intel’s General Manager of the Architecture Group took the stage. He began his talk with a few words about computing challenges of the future. He talked about the immense amounts of data that will need to be processed in the future and the multitude of difference devices that will need to seamlessly access the data.

This is your brain, on Intel -
Mr. Perlmutter also told a story about one of his daughters, who once told him she would like to be able to “record her dreams”. He joked that recording dreams would be a complex problem (obviously), but hinted at PC brain interfaces and mentioned that it may not be impossible at some point in the future. Using Sandy Bridge as his reference point, he mentioned that the chip is comprised of about 1 billion transistors and that the human brain is comprised of about 100 billion neurons. Mr. Perlmutter said, processors with 100 billion transistors are probably about 10-11 years out, and drew parallels between the potential compute performance of processors with that many transistors vs. the human brain.

He then moved on to talk about other interface possibilities and about the need for intuitive interfaces. Mr. Perlmutter then brought out a representative from a company called GestureTek who showed off a gesture tracking interface that used inexpensive 3D camera. Using the interface, users are able to simply make gestures in front of the screen to control interface elements. GestureTek explained that the increased performance offered by Sandy Bridge, in addition to the decreased cost of 3D camera will make this technology affordable to consumers in the not too distant future.

Sandy Bridge, Lord of The Ring - 

Dadi then moved on to talk about some of the specific features of Sandy Bridge, its design, and Turbo 2.0. He explained that Sandy Bridge is outfitted with a high speed / low latency ring bus that helps bring all of the core elements together. Initial Sandy Bridge processors will use an 1155 pin socket and be paired to upcoming 6-series chipsets. Desktop and mobile SB processors will initially be offered with up to four cores and that all of the cores, in addition to the DX10.1 class GPU, can boost their speed using Turbo 2.0 depending on thermal and power restraints. He also mentioned, however, that SB can briefly Turbo boost beyond TDP in some instances and that it is not limited to just one or two cores.