Intel Skylake Architecture Preview Quick Take From IDF 2015

Intel is still keeping a number of details regarding its complete Skylake microarchitecture and product line-up under wraps for a few more weeks, but at a public session at IDF, some of the key technologies and design updates introduced with Skylake were discussed.

During the session, Julius Mandelblat, Senior Principal Engineer at Intel, talked about changes to the CPU core in Skylake, along with some improvements made to the interconnects and memory interface, power and thermal characteristics, and platform level enhancements. Performance wasn’t discussed in detail, however; we’ve already tested the Skylake-based Core i7-6700K processor for desktop systems, so some early real-world numbers are available here.


Virtually every aspect of Skylake has been improved versus the previous-gen Haswell microarchitecture. I/O, Ring Bus, and LLC Throughput has been increased, the graphics architecture has been updated to support DX12 and new eDRAM configurations, it has an integrated camera ISP, support for faster DDR4 memory, and more flexible overclocking features. All of these things culminate in a processor that offers higher IPC performance and improved power efficiency.


At the front end, Skylake features an improved branch predictor with higher capacity, a wide instruction supply which support up to 6 µops per clock, faster pre-fetch, and deeper out of order buffers. The execution units have been beefed up as well, and offer improved latency and lower-power.


There is also more load/store bandwidth in Skylake, the Prefetcher has been improved and cache management has been overhauled with a higher-performing algorithm and better handling of page misses. To put all of this more simply, Skylake can have more instructions in flight at any given time, IPC performance has been increases through cache and front end optimizations, and power efficiency has been improved as well. In fact, Skylake will scale all the way down to 4.5 watts and up to 91 watts.


All told, the Out-of-order window size has been increased to 224 vs. 192 in Haswell. In-flight loads remains the same at 72, but stores are increased to 56. Schedule entries are increased significantly, up to 97 vs 60 in Haswell and the Integer register file is larger as well. The FP register file, however, remains the same. The Allocation Queue in Skylake is now 64/thread, which has also been increased over Haswell.