AMD EPYC 7000 Series Architecture Review
Due to the fact that EPYC and Ryzen feature the same Zen-based cores, there weren’t many new architecture details revealed at the launch event. Some clarity was provided about how the cores and sockets are linked and a few additional disclosures were made regarding power management and security-related features though.
Because we’ve already covered the Zen microarchitecture in depth here at HotHardware, we won’t be doing so again here. If you would like a refresher, however, we would suggest perusing a few recent articles including AMD’s initial Naples announcement, and our Ryzen platform coverage and Ryzen 7 launch article. In those articles, you’ll find information regarding AMD’s Infinity Fabric, and Zen-specific features like SenseMI, XFR, Precision Boost, Pure Power, Neural Net Prediction, cache structure, and other architectural advantages Zen has over Bulldozer.
Ultimately, what all of the enhancements built-into the Zen microarchitecture amount to is a massive 52% (give or take) IPC improvement over AMD's previous-generation Bulldozer microarchitecture. Zen is also much more power efficient and has an updated feature set, with support for additional instructions.
EPYC 7000 series processors support many standard instructions sets including AVX and AVX2, BMI1 and BMI2, AES, RDRAND, SMEP, and a few others, including a couple of AMD exclusives. There is no support for AVX-512, however. According to AMD, the power to performance trade-off wasn't there and it made the decision to skip AVX-512 support.
Another key benefit of the Zen microarchitecture over AMD's previous generations is improved latencies throughout the chip. Cache latency in particular is significantly improved. AMD claims that Zen's L2 TLB, L2, and L3 latencies are on-par with, or slightly better than Intel's Broadwell microarchitecture and they're in a another league altogether versus Bulldozer.
EPYC has an integrated server controller hub as well. The SCH has four USB ports built in, along with a platform clock generator, dual SMBus ports, six I2C ports, timers, interrupts, and other general purpose I/Os. Integrating the SCH gives AMD the ability to eliminate the requirement for a PCH, which simplifies and streamlines partner board designs.
Like some of AMD's previous generation processors, the EPYC 7000 series also features a built in Platform Security Processor. But, EPYC also features hardware memory encryption to prevent against physical memory attacks. Secure Memory Encryption, or SME, is designed to defend again unauthorized access to memory, but still allows for hardware devices like access encrypted pages through DMA (direct memory access). This feature adds a small amount of latency (we're told roughly 7ns), but the overall performance penalty is in the neighborhood of only 1.5%.
Tying all of this technology together is AMD's Infinity Fabric, which we'll discuss next.