A Closer Look At The Athlon II X4
The Athlon II X4 series is based on a new spin on the familiar Deneb core used in existing Phenom II processors, called Propus. The new Propus core is essentially a trimmed down Deneb with the L3 cache removed.
A quick peek with the latest version of CPU-Z shows us that unlike the dual-core Athlon II X2s which benefit from increased L2 cache to compensate for the lack of L3 cache, quad-core Athlon II X4s have to make do with the same amount of L1 and L2 cache as Deneb. Just like Deneb-based Phenom II processors, the Athlon II X4 630 and 620 are equipped with 64KB of L1 instruction and 64KB of L1 data cache per core, for a total of 512KB of L1. Each core also has 512KB of L2 data cache, for a grand total of 2MB L2 cache. Unlike Deneb which has 6MB of L3 cache, we see that Propus has none at all.
The reduction in cache means the new Propus core is significantly smaller than Deneb at just 169mm2, compared to Deneb's 258mm2. The drastic reduction in size means the new Propus cores are much cheaper to build and AMD seems to be passing the savings down to consumers.
While the removal of Deneb's 6MB of L3 cache results in drastic die size savings, it comes at the cost of performance. As we saw in our Athlon II X2 review, cutting out the L3 cache isn't debilitating, but it does hurt performance in certain applications.
| 169mm2 Propus die
|| 258mm2 Deneb die|
Other than the removal of L3 cache, the Propus core is otherwise identical to Deneb. As you can see in the images of the Propus and Deneb dies above, the Propus appears to literally be a Deneb with the L3 cache chopped off.
In fact, some of the early Athlon II X4 engineering samples that are currently floating around are actually 258mm2 Denebs cores with the L3 cache disabled and not true 169mm2 Propus cores. Some users who have gotten their hands on these chips have even claimed to have been able to unlock the L3 cache. However, if you have hopes of doing the same, you'll have to hurry as all future Athlon II X4 stock will be made from Propus cores with the L3 cache physically removed.