NVIDIA Vera CPU Performance Claims And Olympus Core Architecture Revealed

NVIDIA just shared additional details regarding its upcoming Vera data center server processors at SIGGRAPH 2026, ahead of AMD's Advancing AI event which kicks off this week. The information offers a deeper look at the company's design philosophy and its performance goals ahead of the CPU's launch alongside its Rubin AI accelerators. While NVIDIA has previously disclosed Vera's headline specifications, this newly revealed presentation expands on the architectural direction behind the processor and includes several new performance claims aimed squarely at modern x86 server CPUs.

NVIDIA's Agentic AI-First CPU Design Philosophy

The central message throughout the presentation is that Vera has been designed specifically for emerging agentic AI workloads, as opposed to traditional cloud computing. NVIDIA argues that because AI agents repeatedly transition between GPU inference and CPU-based execution and orchestration, with a single session potentially making hundreds of trips between the accelerator and host processor, this places renewed emphasis on CPU latency, memory performance, and per-core responsiveness rather than simply maximizing total core count or instruction throughput.


To support that argument, NVIDIA contrasts what it describes as the "frequency-optimized" CPUs that dominated data centers before the rise of hyperscale cloud computing with today's "scale-out" processors, which prioritize high core counts and throughput. The company argues that cloud economics pushed CPU vendors toward chiplet-based designs that maximize core density and manufacturing efficiency, but place less emphasis on per-core performance and latency-sensitive workloads.

NVIDIA Details The 'Chiplet Tax' And Opts For A Monolithic Design

NVIDIA is particularly critical of modern chiplet architectures, repeatedly referring to what it calls a "chiplet tax." According to the presentation, distributing cores across multiple compute chiplets increases data movement, reduces effective memory bandwidth, and introduces additional latency as traffic traverses multiple dies. Although NVIDIA only ever names AMD in the footnotes, one slide illustrates this concept using a diagram that closely resembles the company's upcoming EPYC Venice architecture, complete with 12-core compute chiplets surrounding a central I/O die.


Instead, Vera adopts a monolithic design connecting cores and cache to memory and other I/O using NVIDIA's second-generation Scalable Coherent Fabric. NVIDIA claims the fabric delivers up to three times the core-to-core bandwidth of competing chiplet architectures while eliminating many of the latency penalties associated with crossing die boundaries. 


Rather than simply claiming the fastest single-threaded CPU, NVIDIA repeatedly describes Vera as delivering "max single-threaded performance at scale." The distinction is deliberate. Instead of optimizing solely for lightly loaded benchmark runs, NVIDIA argues that Vera is designed to maintain high per-core performance even when deployed in servers with dozens of active cores, a scenario where the company believes today's throughput-oriented server processors begin to sacrifice latency and responsiveness.

The processor is also paired with an LPDDR5X memory subsystem using SOCAMM2 modules rather than conventional server DIMMs, with NVIDIA claiming 40% lower memory latency, three times the memory bandwidth per core, and as much as five times greater bandwidth-per-watt efficiency than current DDR5-based server platforms.

NVIDIA's Olympus Core Sports A Very Wide, Custom Arm Architecture

NVIDIA further includes one of the first diagrams of Vera's Olympus CPU core. While the block diagram is nowhere near a full architectural disclosure, it confirms a conventional out-of-order pipeline (unlike Denver) with branch prediction, register renaming, reorder buffer, execution schedulers, dedicated load/store hardware, and a massive 10-wide instruction decode stage, putting it in the same ballpark as Apple's M5-class cores in terms of frontend width.

NVIDIA describes Olympus as being designed for "high per-core performance and spatial multithreading for throughput," although the presentation does not elaborate on what "spatial multithreading" actually means; it could simply be marketing-speak for the two-way Simultaneous Multi-Threading (SMT) that Vera is known to support, or it could be something more complex. We'll probably learn more as we get closer to availability.


Beyond the architectural discussion, NVIDIA makes several ambitious performance claims. The company states that Vera's Olympus core delivers "2X performance," although the presentation does not actually specify what it's comparing against; we asked and were told the performance comparison is versus today's x86 server processors.


Customer benchmarks shown later in the deck compare Vera against existing Intel Xeon and AMD EPYC platforms across several real-world workloads rather than standardized CPU benchmarks, with reported gains ranging from approximately 1.5× faster job completion in Perplexity's sandboxing environment to as much as 6× lower streaming latency for NYSE data processing workloads and 7× higher performance in selected agentic simulation workloads at Los Alamos National Laboratory.


Taken together, this new presentation from NVIDIA makes it clear that company is not positioning Vera as a conventional server CPU. Instead, the company argues that AI agents fundamentally change what matters in processor design, shifting the focus away from maximizing throughput per dollar and toward minimizing latency throughout the repeated CPU-GPU execution loop. Whether these claims translate into broad performance advantages in the real world remain to be seen and will ultimately depend on independent benchmarking, but the presentation provides the clearest picture yet of how NVIDIA intends to differentiate Vera from existing x86 server processors as AI infrastructure continues to evolve.