AMD Zen 7 Leak Reveals Major IPC Gains And Huge Cache Upgrades

Whatever you think of Moore's Law is Dead, he's just dropped a massive new leak seemingly revealing tons of supposed details about AMD's upcoming Zen 7 architecture and the products that will be based on it. As always, take these leaks with a grain of salt, but if the details hold true, Team Red is preparing a generational leap that relies heavily on advanced 3D stacking, bleeding-edge silicon, and monumental amounts of cache.

At the heart of the Zen 7 family, across server, desktop, and mobile, is TSMC's upcoming A14 node. According to the leak, this foundation, along with architectural changes, is projected to deliver a staggering 15% to 25% IPC uplift over the still-unreleased Zen 6. AMD is also leaning hard into the AI race, outfitting the "Classic" Zen 7 cores with built-in acceleration that promises a 4x uplift in FP8 and a 2x boost in INT8 processing per cycle.

The seventh-generation EPYC processors, codenamed "Florence," are where AMD's new die-stacking strategy truly shines. Florence apparently tops out at an immense 288 cores, achieved by combining two high-end "Dwarka" I/O dies, dual "Mathura" memory controller dies, and eight unique "Steamboat" CCDs that are described as "C3Ds". Steamboat is a radical departure that has no L3 cache on the CCD itself. Instead, it pairs the "C3D" with a dedicated 3D-stacked cache die underneath that provides a massive 7MB of L3 per core, allowing top-tier EPYC configurations to wield nearly 2GB (2016 MB) of total L3 cache.

For consumers, the Zen 7 desktop lineup ("Grimlock Ridge") maintains backward compatibility with Socket AM5. The standard high-end "Silverton" CCD reportedly bumps core count once again, from the twelve cores of Zen 6 "Olympic Ridge" on up to 16 cores, with 64MB of on-die L3, but it can also support second-generation 3D V-Cache to reach a staggering 224MB of L3 per chiplet. Arguably the biggest change in the standard core is the move to 2MB of L2 cache per core, which is double what is present on Zen 5 and, as far as we know, Zen 6.


Because these Zen 7 components are highly modular, it is apparently possible, in theory, for AMD to drop two 36-core Steamboat CCDs onto an AM5 substrate for a 72-core desktop chip. However, even MLID notes this is incredibly unlikely for standard consumers and would likely be reserved for embedded platforms or extreme halo products if AMD simply wanted to flex on Intel, perhaps as a response to Intel's 52-core Nova Lake chips.

Meanwhile, as you'd expect, the mobile sector may see the most dramatic performance-per-watt improvements. The mainstream "Grimlock Point" relies on a monolithic I/O die that, according to MLID, houses 12 base cores (four Classic, eight Dense, similar to Strix Point), with options to scale up by adding a smaller 8-core "Silverking" chiplet. Reportedly, Zen 7 scales better at low power than Zen 6; at an ultra-low 3W per core, these mobile chips are said to be up to 36% faster than Zen 6.

Then, at the top end, the enthusiast "Grimlock Halo" platform could push laptops up to a staggering 36 total cores (with eight Zen 7 cores, twelve Zen 7C cores, and a pair of "Silverking" eight-core CCDs) alongside a massive on-package GPU of some kind. MLID doesn't have many details about Grimlock Halo yet, but says he's preparing another leak with more information, which should be interesting.

While AMD has reportedly scrapped its experimental "2-hi" double-stacked cache designs, the innovations that the company is bringing to market are nothing short of wild. The only release date Tom gives for any of this is for EPYC "Florence", the Zen 7 parts, which are slated to enter production in mid-2028 thus setting the stage for a late-2028 launch.