Intel’s Exascale HPC Revolution and Xeon Phi

Last month, Intel brought us out to the Texas Advanced Computing Center (TACC) in Austin to brief us on their latest and greatest foray into high-performance computing (HPC) and exascale level processing performance.

Parallel Computing and the Road to Exascale
There are mountains of problems that need to be solved and a myriad of insight to be gained, in fields from the sciences to national security, that require HPC and highly parallel processing to most effectively and efficiently solve. Parallel processing is what the HPC space is all about, and when large amounts of data can be processed and complex problems solved, it can help researchers move from the concept phase to the results phase more quickly.


Intel’s John Hengeveld said that Big Data is like drilling in an oil field; it digs through data and extracts records, and HPC is the pump that sucks it out. Ideally, Big Data and HPC create streams of information that can be used to accomplish great things. HPC can use Big Data to create insights into data aggregation, data analytics, data visualization, and interactive visualization and simulation, among a multitude of other things. And Hengeveld noted that these are all highly parallel problems that require parallel processing to solve in a timely manner.

Intel’s Xeon E5 architecture established a foundation for parallel processing for the company and could realistically deliver performance at the petascale level, but the giant leap forward to exascale computing was not looking like a reality in the near future; with the processing paradigm inherent in the Xeon line, the power demands and processing capabilities wouldn’t allow it.

To address this problem, Intel spent years developing its Many Integrated Core (MIC) technology. In a nutshell, the MIC architecture uses many, smaller low-power cores instead of a few full-blown, high-powered cores to accomplish processing tasks, thus enabling parallel processing on a much greater scale. The fruit of that labor is the new line of Intel Xeon Phi Coprocessors.


The Future of HPC For Intel: Xeon Phi
Working in tandem with Xeon E5 processors, Xeon Phi coprocessors can deliver on the promise of exascale computing today. According to Intel, the most efficient path to exascale computing is Xeon + Xeon Phi.

The Xeon Phi coprocessors are designed to deliver all the advantages of Intel’s architecture, including familiar programming environments and performance tuning tools and advanced power management technology, while also offering the performance of an add-in accelerator. To be clear, though, Xeon Phi is not an accelerator; it’s an actual many-core CPU. It can (theoretically) even run an operating system, although it looks more like a cluster of computers on a chip.

In practice, different users will use different combinations of Xeon/Xeon Phi depending on the problems that need to be solved--for example, one customer might run one Xeon and two Xeon Phis, while another would have two Xeons and a lone Xeon Phi (or any other possible combination). The flexibility of offering the Xeon Phi as a PCI Express add-in board gives customers the ability to configure their servers to best suit the needs of their parallel computing workloads.