AMD Spider Platform - Phenom, 790FX, RV670
At the heart of AMD's Spider platform is the native quad-core Phenom processor. Phenom is the brand name given to processors based on the Agena core, which is virtually identical to the Barcelona core used in the recently released AMD quad-core Opterons.
;)
;)
;)
In a quad-core Phenom processor, each of the four cores is outfitted with 64K of L1 instruction and 64K of L1 data cache, for a total of 512K of L1 cache per CPU. The L2 cache compliment of each core is 512K, for a total of 2MB. New to the Barcelona and Agena cores is 2MB of dynamically shared L3 cache. Unlike L1 and L2 caches, which are exclusive to each execution core (data in Core 1’s L2 cache cannot be accessed by Core 3, for example), the L3 cache is shared among all the cores. Also new to Barcelona and Agena is a 128-bit wide memory controller that can be configured as dual independent 64-bit channels to allow for simultaneous read and write memory operations.
Currently, all Phenom processors will be built in AMD’s Dresden, Germany facility using the company’s 65nm SOI (silicon on insulator) manufacturing process. Each quad-core die is comprised of approximately 463M transistors (about 357M less than Intel’s quad-core Yorkfield) and is about 285mm2 in size.
;)
;)
;)
Looking deeper into the Phenom's native quad-core, single die architecture, we've learn that the cores themselves have been revamped considerably for efficiency and performance. Here are a few of the key salient points of Phenom's new core micro-engines:
- A new floating point scheduler now supports 36 128-bit operations
- Support for 128-bit SSE operations, an upgrade from the previous 64-bit architecture
- Two SSE operations and one SSE move can be processed per cycle
- Processor instruction fetch has been increased from 16 to 32 bytes
- Advanced branch prediction with built in a 512-entry indirect branch predictor
- Data cache bandwidth has increased from 1 x 64-bit loads per cycle to 1 x 128-bit loads per cycle
- L2 cache / memory controller bandwidth has been increased from 64-bits per clock to 128-bits per clock
- HyperTransport 3.0 Support for up to 20.8GB/s of raw bandwidth
In addition to the enhancements listed above, Phenom processors support dynamic clock gating on a per-core basis. Though core voltages won't be managed independently, the clock speed of each core can throttle back when idle, which could in turn provide significant power savings. And AMD's "CoolCore" technology allows for functional blocks of each core to be shut off when not in use, further improving power efficiency. You may have heard of AMD's "Dual Dynamic Power Management" technology referred to as "split power planes" in the past.
We should note that to fully take advantage of AMD's "Dual Dynamic Power Management" technology, a next-gen platform must be used. Users that drop a Phenom into an existing socket AM2 platform will not have support for split power planes, because current motherboards lack the necessary support.
