AMD Phenom X4 9850 B3 Revision
Introduction and Specifications
It doesn't take a genius to figure out that AMD's initial Phenom processor launch didn't go exactly as planned. The first batch of retail-ready Phenom processors were clocked lower than expectations and in the days leading up to the launch, the now infamous TLB bug reared its ugly head. If you're not aware, all initial Phenom and Opteron quad-core processors based on the Barcelona architecture were plagued by an errata that could cause a system crash under certain circumstances. The errata involves the processor's translation lookaside buffer or "TLB" and L3 cache. Keep in mind, every processor has some sort of errata, but it usually isn't cause for concern, nor does it manifest itself in any real-world application performance. In many cases processor errata can be worked-around via BIOS or software patches and end users are none the wiser. With the Phenom's TLB errata though, working around the problem involved a significant performance penalty.
Obviously aware of the problem, AMD's engineers immediately went to work crafting a new revision of the native quad-core Phenom silicon that resolved the TLB errata. And today that new revision is ready. Quad-core Phenom processors based on the new B3 revision silicon should be hitting store shelves in the not too distant future. In addition to resolving the TLB bug, AMD is also unveiling some higher clocked Phenoms and tri-core and low-power models too.
We've got AMD's latest and greatest Phenom processor, the Phenom X4 9850, on the test bench and have our findings posted for you here. First up, the specifications...
AMD Phenom Retail Box
 |
|
| Model / Processor Frequency: | AMD Phenom Processor Model X4 9850 / 2.5GHz |
| L1 Cache Sizes: | 64K of L1 instruction and 64K of L1 data cache per core (512KB total L1 per processor) |
| L2 Cache Sizes: | 512KB of L2 data cache per core (2MB total L2 per processor) |
| L3 Cache Size: | 2MB |
| Memory Controller Type: | Integrated 128-bit wide memory controller, capable of being configured for dual 64-bit channels for simultaneous read/writes |
| Memory Controller Frequency: | Up to 2.0GHz with Dual Dynamic Power Management |
| Types of Memory: | Support for unregistered DIMMs up to PC2 8500 (DDR2-1066MHz) |
| HyperTransport 3.0: | One 16-bit/16-bit link @ up to 4000MHz full duplex |
| Total Processor Bandwidth: | Up to 31.5 GB/s bandwidth |
| Packaging: | Socket AM2+ 940-pin organic micro pin grid array (micro-PGA) (backward compatible with Socket AM2) |
| Fab location: | AMD's Fab 36 wafer fabrication facilities in Dresden, Germany |
| Process Technology: | 65nm (.065-micron) Silicon on Insulator (SOI) |
| Approximate Transistor count: | approx. 450 million (65nm) |
| Approximate Die Size: | 285 mm2 (65nm) |
| Nominal Voltage: | 1.1-1.25 Volts |
| Max Ambient Case Temp: | 70 degrees Celsius |
| Max TDP: | 125 Watts |
| ACP: | *to be announced after launch |
| Future Memory Controller Note: | Future 45nm processors versions are planned to include support for DDR3 memory |
;)
;)
AMD Phenom X4 9850
Save for its unique markings, the new AMD Phenom X4 9850 looks exactly like any other socket AM2+ processor outfitted with AMD's standard heat spreader. The chip uses the same packaging and socket as current Phenom processors; it is only the silicon underneath that has changed.
The AMD Phenom X4 9850 is a 2.5GHz processor manufactured using AMD's 65nm Silicon on Insulator process technology. The chip has a Max TDP of 125W and it is a "Black Edition" product, which means its multiplier is unlocked for more flexible overclocking. New to the Phenom X4 9850 is full support for a 2.0GHz memory controller and HT 3.0 frequency with Dual Dynamic Power Management technology. Although AMD had previously mentioned support for a 2GHz memory controller and HT3.0 link frequency, the memory controller in the initial batch of Phenoms clocked in at 1.8GHz. Also note the "X" designation has returned to the product name. With the new tri-core processors about to hit as well, AMD felt this additional designation would make it easier to discern the number of cores available in the CPU. Another move designed to help differentiate their product offerings is the "50" in the model number. To keep things simple, a "50" in the last two digits of the model number designates a processor based on the B3 revision core.
