NASA’s New RISC-V Space Chip Offers 100x Performance Boost for Future Mars Missions
JPL reports that the High‑Performance Spaceflight Computing (HPSC) SoC, developed in partnership with Microchip, has passed early functional testing and is showing performance far beyond today's flight‑qualified processors. The HPSC family includes both a radiation‑hardened version for deep‑space and long‑duration missions and a radiation‑tolerant variant aimed at commercial low‑Earth‑orbit satellites, giving mission designers a scalable tool for everything from small science probes to crewed lunar systems.
The HPSC SoC uses modern open architecture and multi‑core designs to bring vector processing and deep‑learning accelerators into spaceflight hardware. Some reports claim that the SoC is comprised of 12 RISC‑V primary cores and eight SiFive Intelligence X280 cores, plus another four unspecified RISC-V cores. The chip integrates cores, hardware accelerators, memory, and networking on one package. NASA and Microchip say the design approach "delivers over 100 times” the computational capacity of existing spaceflight computers. Moreover, JPL tests have shown that some configurations can operate at roughly 500x the performance of legacy rad‑hard parts in lab benchmarks.
Increasing processing performance is crucial because missions are now collecting orders of magnitude more data (e.g. high‑resolution imagery, laser altimetry, and complex sensor suites) and need to operate at low-latency in siturations when milliseconds count, such as handling autonomous landings, hazard avoidance, and onboard science triage that decides what data to send home.
With HPSC, spacecraft could potentially run advanced navigation algorithms, real‑time image processing, and machine‑learning inference on board, reducing latency and cutting down costly communications with Earth.
Since cosmic rays and solar particles can flip bits or disable chips permanently, the HPSC pairs radiation‑hardened‑by‑design techniques with fault‑tolerant software and redundant hardware paths so a single strike won't end a mission.
Another interesting aspect is the public-private nature of this project. It involves NASA's investments combined with Microchip’s commercial development resources, accelerating a timeline that aims to get next‑generation processors into flight test more quickly than traditional government‑only projects.
If the chips continue to meet radiation, thermal, and lifetime reliability expectations in extended testing, they could enable missions that today are impossible or too risky, such as precision autonomous landings on Mars or quick decision capabilities during long cruise phases, to name a few.
