Intel Plans 14A2 Node With Dual Side Power To Battle TSMC And Samsung

The PowerVia back-side power delivery network (BSPDN) technology that Intel pioneered with its 18A fabrication process is brilliant, because separating power lines from data lines offers tremendous benefits to chip designers in terms of layouts. However, there's a major challenge: backside power delivery means having to use extremely tiny nano-Through-Silicon Via (nTSV) connections inside the chip. When the power delivery wires are so tiny, resistance increases, and thus voltage droops. To combat this, Intel's 14A process will apparently get a revision known as 14A2 that supports hybrid power delivery ("dual side power") with power lines on both sides of the chip.

This news comes to us from the Korean-language Electronic Times, better known as ETNews. That site writes that Intel originally intended to rely exclusively on its dedicated "PowerDirect" backside power network across the baseline 14A family. However, as the foundry pushes to deliver a 1.3× density boost over 18A, the follow-up 14A2 process node is running into physical boundaries that demand an architectural rethink.


According to the report, to justify the astronomical costs of High-NA EUV lithography tools, Intel is aiming to shrink the pitch of its lowest metal layer (M0) from 28nm on baseline 14A down to an ultra-dense 21nm on 14A2. When interconnects shrink below 21nm, electrical resistance skyrockets due to quantum surface scattering. The tiny nTSVs carrying current from the back of the wafer simply can't handle the power density required by these densely packed transistors. The result is severe IR drop (voltage sagging) that can lead to clock instabilities and power failure.

Intel's proposed fix is a hybrid compromise. The Backside Power Delivery Network (BSPDN) remains the main pipeline for electricity, while portions of the front-side metal layers will be re-allocated to assist with supplemental power delivery and clock signals. While stealing front-side real estate back from signal wires re-introduces routing complexity, industry analysts interpret it as a necessary compromise to squeeze out a functional 21nm process spec.

Intel's execution schedule doesn't leave much room for missteps. The baseline 14A node is slated for risk production in 2028 and volume production in 2029, with version 0.9 of its Process Design Kit (PDK) supposed to land in potential customers' hands this October. Intel will then have a roughly 18-month window to lock in firm commitments from major fabless giants.


Meanwhile, the competition is moving fast. For TSMC's part, having already hit its stride on 2nm, TSMC plans to ship commercial A14 (1.4nm) chips in 2028, right as Intel 14A enters risk production. Meanwhile, Samsung plans to launch SF2Z, its 2nm revision featuring backside power, in 2027. Crucially, Samsung is layering backside power onto a Gate-All-Around (GAA) architecture it has already refined across three generations, which might mean far less integration risk than Intel.

Intel's reported move to Dual-Side Power on 14A2 is just another example of the brutal reality of sub-2nm chip manufacturing, which is that silicon scaling is no longer just about shrinking transistors, but surviving the increasingly bizarre physics of powering them. Whether this hybrid workaround gives Intel the stability it needs to win over major fabless clients in the next 18 months will be the ultimate test for Intel Foundry.