AMD Zen 6 Takes A Page From Intel With New Low-Power Cores
To be fair, Badole doesn't actually mention Zen 6 anywhere, but it's the reasonable assumption. That's both because none of AMD's extant processors have "Low Power" cores, and also because many prior Zen 6 leaks pointed to the existence of exactly that on, at least, "Medusa" mobile processors, if not also many other chips based on the Zen 6 architecture. That includes the semi-custom processors that are reportedly in the works for the PlayStation 6 as well as the next-gen Xbox, code named "Project Helix," and possibly even the Olympic Ridge desktop CPUs, though that part's more uncertain. The rumor goes that many Zen 6 processors will include two Zen 6 LP cores in the I/O die, allowing the system to come up even if no CCD is attached.
As we alluded to in the headline, AMD isn't exactly breaking new ground here with the addition of a third core type to its processors, and not even in the x86 world. Indeed, besides the many Arm processors that have had three tiers of CPU cores in the past, Intel's had "LP E-cores" since its first-generation Core Ultra processors, perhaps better known as "Meteor Lake". On that chip, the two LP E-cores lived on the SoC tile, but newer Intel chips have moved the low-power island onto the Compute tile for improved efficiency; they simply don't share the same ring bus or clock domain as the P-cores or E-cores, allowing those parts to be fully shut down.
Given that, it might actually be a little surprising that AMD are the ones adding this support to the Linux kernel; Intel has historically been more active than AMD in its addition of kernel patches, so why didn't the company try to advocate for support of a third core type in the x86 part of the kernel to begin with? Well, it likely comes down to how the two companies design their silicon and how it interfaces with the OS.
Intel's approach relies on the Intel Thread Director and Enhanced Hardware Feedback Interface, where it dynamically feeds performance and efficiency values to the kernel, bypassing hard-coded topology labels. AMD's route is quite different; instead of using a hardware coprocessor like the Thread Director, AMD prefers the operating system to know exactly what the hardware layout looks like as soon as it boots. AMD processors enumerate their core type using a CPUID function, and without these patches, Linux sees a third core type, has no idea what to do with it, and just comes back "unknown", which is likely going to cause poorly defined behavior.
Notably, these changes are only coming to the x86 side of the Linux kernel; the Arm kernels have been handling multiple core types for years already. Instead of hardcoded tags, Arm relies on a unified framework of Capacity and Energy-Aware Scheduling (CAS/EAS) that treats all cores as a gradient of performance numbers. In the end, to the end-users, the approach to heterogeneous core scheduling doesn't really matter. Ultimately what matters is going to be the benchmark performance, which we'll be happy to present for you once these parts hit store shelves, likely early next year.
Shout out to Phoronix for the spot!
