AMD Announces EPYC 9006 CPUs, Instinct MI400X GPUs, And More At Advancing AI 2026
AMD's EPYC 9006 Series Has A Server CPU For Everyone
We'll start with Venice. AMD hasn't shared a ton of technical details about the Zen 6 core with us yet, but we can tell you that the EPYC 9006 Series processors will come in variants ranging from 8 to 256 CPU cores (that's physical cores, not threads), it will come in versions with and without 3D V-Cache for up to 1152 MB of L3 cache in a single socket, and it'll be available in at least one variant with LPDDR5X memory. They're all branded "EPYC 9006", so prepare for some alphabet soup.
EPYC 9006 SP7 is the core of the processor family. These are the "full-fat" EPYC chips, with up to 256 cores per socket and up to 5 GHz clock rates. The 256-core models are using Zen 6c dense cores; for the hot-clocked chips, you'll want to look at the "HF" variants that come with up to 96 regular Zen 6 cores. TDPs go as high as 600 watts, which is pretty spicy. For memory, you have your choice of 16 channels of DDR5 RDIMMs at up to 8 GT/s or 16 channels of DDR5 MRDIMMs at up to 12.8 GT/s. These parts come with up to 128 lanes of PCI Express Gen 6, and they support additional memory expansion via CXL 3.1.
Customers who won't be needing all that can grab an EPYC 9006 SP8 chip, which AMD describes as being "built for efficient, right-sized performance". These are smaller parts, much like the EPYC 8004 family that came before, intended for edge compute and power-constrained environments, or simply anyone who wants a latest-generation EPYC chip and all that entails, but doesn't need all the cores or connectivity of the big iron. These parts come with between 8 and 128 CPU cores.
Alternatively, for those that need more than the regular EPYC 9006 parts, there's EPYC 9006X SP7. These chips are, as you could probably guess if you know anything about EPYC branding, equipped with AMD's 3D V-Cache. AMD says these parts are made for HPC, technical computing, and data-intensive workloads that benefit from high cache and memory bandwidth. Interestingly, AMD promises the highest clock speeds on these chips; up to 5.15 GHz apparently.
If you're concerned about power, the EPYC 9006 LP (formerly codenamed "Verano") parts are purpose built to serve as AI host node CPUs for rack-scale AI systems. They use LPDDR5X memory—up to 24 channels of it, with field-replaceable SOCAMM2 modules, providing absolutely immense memory bandwidth. Like the "Venice" chips, Verano also supports Unified Power Provisioning, Utilization-Based Power Scaling, and Frequency-Adaptive Spectrum Technology to help with power management and quality of service.
Some chips are shipping this year, but new parts will launch throughout next year.
As far as performance goes, AMD claims that the new EPYC 9006 processors offer as much as 70% increased performance over the previous generation, which is pretty decent even when you take into account the 33% increased core count on the top-end. The company also claims to beat Intel's flagship 128-core Xeon 6980P CPU by as much as 245% in Agentic AI workloads, and also claims to handily dispatch Amazon's Graviton 5 CPU with 192 cores, although it was apparently beating those chips already with its EPYC 9005 "Turin" CPUs. As always, you'll want to wait for third-party benchmarks to validate these vendor supplied numbers.
The CDNA 5-Based Instinct MI455X Steps Up Size And Smarts
On the GPU front, the Instinct MI400 family is presently composed of the Instinct MI455X for ultra high-end AI workloads and then the MI430X, which is more targeted at HPC. The MI455X is getting all the attention today, as unsurprisingly, AMD's presentation is all about AI. This is an absolute beast of a GPU, so much so that AMD CEO Dr. Lisa Su said unambiguously that it is the highest-performing AI GPU in the world. Competitor NVIDIA isn't standing still, so AMD pulled out all the stops on this thing.
Where the MI355X had 288 GB of HBM3e memory, the MI455X has 432GB of HBM4. (No LPDDR5X, despite the rumors.) The RAM is clocked considerably higher, and the interface is 50% wider too, together giving the new chip some 23.3 TB/second of memory bandwidth. That's nearly 3x the previous generation parts. The compute throughput numbers are impressive, too: over 20 PFLOPs (that's petaflops, or 1,000 teraflops) of MXFP8 performance, and if you crunch your model down to MXFP4, that number doubles.
AMD didn't just achieve these performance figures by throwing a bigger GPU at the problem, though. The MI455X moves to the CDNA 5 architecture which seems to be quite a radical departure from the previous generation. CDNA 5 drops the Wave64 structure of last-gen in favor of a more nimble native Wave32 design that, according to AMD, means reduced instruction latency, reduced branching penalties, and reduced register pressure. Combined with the move to a huge 96MB local L2 and more than double the scalar registers per SIMD, as well as a new Broadcast Arbitrator that offers up to 4x bandwidth amplification, the new chips are much better suited for latency-sensitive compute, which is exactly what AI agents are.
AMD's Helios Rackscale Solution Turns 72 GPUs Into One
Which brings us to Helios. This is exactly what you think it is: a direct answer to NVIDIA's impressive NVL72 racks and AMD's latest rack-scale product. The engineering that goes into these products is mind-boggling. Like the NVL72, each Helios rack is functionally a unified GPU. That means all 72 GPUs in the rack can act as a single massive processor. This is "scale-up" taken to its logical conclusion. The standard Helios rack is a 44OU ORW Rack with 18 compute trays and 6 trays that are just switching hardware.
Each compute tray holds four MI455X GPUs that are connected to not only the Venice CPU in the same tray and the 800-Gigabit Ethernet links that enable scale-out performance, but also to a Ultra Accelerator Link over Ethernet (UALoE) network offering 3.6 TB/second of bi-directional bandwidth per GPU; functionally analogous to the competition's NVLink fabric. Interestingly, AMD doesn't give many details about the dual 512-lane 200-Gigabit UALoE switch ASICs doing the bulk of the work in the switch trays.
All told, AMD says that a single Helios rack has 43TB/s of bandwidth to other servers, 260 TB/s of bandwidth between its GPUs, 1.7 PB/s of total HBM4 bandwidth, 31TB of total HBM4 memory, and a mind-bending 2.9 EFLOPS of AI compute. Remember when an entire supercomputer hitting 1-EFLOP was huge news in 2022? This is doing that in a single rack, supposedly. (Of course, that was FP64, and this is probably MXFP4—not exactly the same metric.)
AMD claims that a Helios rack provides 15% more peak FP4 performance, 50% more (HBM) capacity, and 6% more HBM bandwidth versus "the industry leading solution." You may think that's NVIDIA's GB200, but in fact, AMD's actually comparing against NVIDIA's Vera Rubin NVL72, which hasn't actually launched yet. The competition this winter should be pretty fascinating.
