TSMC Confirms Evolutionary 4nm Process Node As It Marches Towards 3nm Chip Production

TSMC Wafer
Seemingly out of left field, Taiwan Semiconductor Manufacturing Company (TSMC) revealed it is planning to crank out chips based on a 4-nanometer manufacturing process. Described as an "evolution" from its 5nm node, TSMC says it is currently in discussions with potential customers about leveraging the node, which fills the gap between 5nm and 3nm.

There is not a whole lot of information available yet. That is because the folks at EE Times caught wind of the previously unannounced node ahead of an official unveling, and TSMC chairman Mark Liu subsequently confirmed to the outlet that 4nm is indeed in the works. However, he stopped well short of discussing the technology in detail. We assume a formal announcement is still coming.

"N4 is an evolution from N5. We're already in business negotiations with customers on N4," Liu told the outlet.

Node analysis can be tricky for a number of reasons. For one, TSMC has several nodes in development or already in use. For example, in addition to N6 (essentially an enhancement of N7), it has N5 and N5P, the latter of which is an enhancement of N5.

N5 is already in production. Looking ahead, N5P and N4 are both part of the same set, as it relates to production capacity. And making matters even murkier is that there is no universal standard for naming nodes. For example, Intel's 10nm technology is roughly on par with AMD's 7nm technology, so it's not a simple matter of a lower number necessarily being better.

In any event, products based on TSMC's 5nm node will arrive later this year, followed by N5P launching in 2022. N4, meanwhile, will go into mass production 2023, assuming everything stays on track.

As it relates to AMD, the company's upcoming Zen 3 processors are expected to remain on 7nm (an enhanced version), despite rumors that they could shift to 5nm. Then sometime next year, Zen 4 chips based on TSMC's N5 node will launch, according to AMD's most recent official roadmap.