Samsung Ramps Production Of 7nm EUV LPP Process With 50 Percent Lower Power Consumption

While Intel has been having problems with mass production of its 10nm product lines, other tech giants like AMD and Samsung are well along in their 7nm endeavors. AMD is currently sampling 7nm EPYC processors, and we're learning today that Samsung has now started mass production of chips using its 7nm LPP EUV process.

LPP and EUV stand for Low Power Plus and extreme ultraviolet lithography technology, respectively. Samsung's 7nm LPP EUV process won't just be used for its own processors (a la the Exynos 9820), but also wide range of customers that rely on its fabs. Samsung says that the usage cases for its 7nm production are endless, ranging from 5G wireless chips to artificial intelligence to automotive applications (i.e. chips for Level 4 and Level 5 autonomous vehicles).

Samsung EUV Line
Samsung EUV Line

Rather than using conventional argon fluoride immersion techniques, Samsung's EUV instead uses 13.5nm wavelength light (versus 193nm) to expose silicon wafers. In addition, EUV allows for the use of a single mask (instead of 4) to create a silicon wafer later. This leads to reduced complexity and cost for production.

So, what does all of this techno mumbo jumbo mean in the end for the customer? Compared to its previous 10nm FinFET process, Samsung says that the new 7nm LPP EUV technology allows for a 40 percent uplift in area efficiency and 20 percent higher performance. Or if customers prefer, the chips can instead be optimized to deliver 50 percent lower power consumption.

“With the introduction of its EUV process node, Samsung has led a quiet revolution in the semiconductor industry,” said Charlie Bae, Samsung Electronics EVP for foundry sales and marketing. “This fundamental shift in how wafers are manufactured gives our customers the opportunity to significantly improve their products’ time to market with superior throughput, reduced layers, and better yields."

Samsung adds that the advances it has made at the 7nm process node allows it to be primely positioned to scale down to the 3nm in the coming years.