A memory chip using this technology would have millions of U-shaped nano-scale wires and sensors built into it. IBM patented its concept in 2004. The effort stalled because actual speeds were much slower than scientific theory predicted. What Meier and his team have achieved is to speed up magnetic region movement along the wire a hundred-fold and to show that such a memory technology is now theoretically possible.
In a chip using this technology, each nanoscale wire would be read sequentially. That means, supposing you have an 8-bit wire, that you would need 8 billion of them to store 1GB of information, together with a billion read/write sensor heads.
Manufacturers would need to achieve very high purity in the nanoscale wires with relatively few atoms. Tolerances would be tiny. Any imperfections cause the speed of the magnetic regions along the wire to slow or stop altogether. Consequently, this research technology would present a massively parallel storage medium of great complexity in terms of manufacture and test if it was to be commercialised.
It will be a very hard manufacturing problem. To allow for imperfections in some nanowires, it would be necessary to over-provision a magnetic racetrack chip so that bad elements could be ignored. Depending upon the imperfection ratio, it would be necessary to over-provision by 10-20% and possibly more...
Like we said, might have an answer.