Qualcomm Validates HBC Silicon With Huge 18x Leap In AI Memory Bandwidth

by Aaron Leong — Monday, November 02, 2026, 10:39 AM EDT

Qualcomm's high-bandwidth compute is proving its worth following internal lab testing — Qualcomm's high-bandwidth compute (HBC) is proving its worth following internal lab testing - Image: Qualcomm

Qualcomm has announced validation its first-generation High Bandwidth Compute (HBC) silicon in the company's San Diego labs, with testing showing 18 times greater bandwidth over DDR5 and five times the efficiency of HBM4.

Computing demands have been changing as LLMs transition from training to large-scale agentic inference, specifically how the latter is bound primarily by memory bandwidth, or rather, how rapidly weight and activation data can traverse the physical space between memory pools and processing units. While high bandwidth memory (HBM) is the current go-to solution, HBM incurs steep thermal, financial, and electrical power premiums due to off-package data movement over millimeter distances. SRAM-based alternatives offer massive throughput but falter on memory capacity and total cost of ownership at rack scale.

Qualcomm's HBC attempts to solve the inference memory wall but placing the memory on top of the compute die — Qualcomm's HBC attempts to solve the inference memory wall but placing memory on top of the compute die - Image: Qualcomm

Enter Qualcomm's HBC architecture, which vertically stacks low-power LPDDR memory dies directly on top of an active AI accelerator base die using direct wafer-to-wafer bonding. By shifting data movement from millimeters to micrometers, the processing logic executes near-memory calculations within the single package, eliminating off-package transfer overhead for operations with low arithmetic intensity.

Physical validation on automated test equipment in San Diego confirmed that the core technology functions as intended under production-representative dimensions using randomized weights and activations. Hardware measurements showed that first-gen HBC achieves an 18-fold increase in effective memory bandwidth compared to LPDDR5X memory implementations. On the energy-efficiency front, HBC delivered over five times the bandwidth-per-watt performance of projected HBM4 specifications. Indeed, the latter score came in slightly below the company's initial 6-fold projections, but still, it's quite the win.

HBC accelerator diagram - Image: Qualcomm

The silicon sample evaluated said lab testing utilized a two-layer DRAM stack bonded over logic, whereas commercial products will feature a four-layer DRAM stack. Built on over a decade of 3D memory integration research, JEDEC standard shaping, and wafer-to-wafer direct bonding experience, Qualcomm has integrated remapping and redundancy techniques into its manufacturing process to mitigate defect propagation across stacked silicon layers.

Qualcomm plans to commercialize HBC technology within its Dragonfly AI portfolio. The first product, the Dragonfly AI250 accelerator platform, is scheduled to sample to enterprise customers and hyperscalers in the first half of 2027. Made for disaggregated inference workloads, a full Dragonfly AI250 liquid-cooled rack sports 38.6TB of system memory capacity and 7.4 petabytes per second of effective memory bandwidth. The company also plans to deploy its custom Oryon-based C1000 server CPU in 2027, followed by next-gen HBC integration in the Dragonfly AI300 platform in 2028.