Intel Diamond Rapids Packs 256 Cores, 16 Core Chiplets And A Huge 1.28GB Cache

by Aaron Leong — Tuesday, August 25, 2026, 10:24 AM EDT

Intel introduces the Xeon 7 Diamond Rapids SoC — Intel introduces Xeon 7 Diamond Rapids - Image: Intel

Intel unveiled key package design and architecture details of its next-generation Xeon 7 Diamond Rapids processors for data center servers, featuring a massive architecture overhaul with up to 16 CPU tiles and 1.28GB of cache specifically to handle data-intensive agentic AI workflows.

Outlined in a Hot Chips 2026 presentation, the flagship Diamond Rapids CPU scales up to 256 performance cores (in an all P-core architecture) paired with a massive 1.28GB pool of Last-Level Cache. To achieve this density and performance (and to position the platform as a direct response to competing hyperscaler enterprise chips), Intel went toward a highly disaggregated chiplet topology built entirely on its own internal Foundry nodes.

The Diamond Rapids design is a multi-tile assembly comprising 22 distinct silicon components where the main package hosts 16 compute core chiplets fabricated on the Intel 18A-P process node, each housing 16 Panther Cove P-cores. These dies are vertically stacked using Foveros Direct 3D hybrid bonding onto four base tiles, manufactured on the Intel 3-T node. Each base tile acts as a high-density interposer and houses a shared 320MB L3 cache pool, providing all 64 cores on that tile balanced and equal, ultra-low latency access to the memory reserve.

Beyond CPU Cores, Interconnect And Packaging Help WIth Diamond Rapids Bandwidth And Efficiency

Diamond Rapids construction - Image: Intel

Communication across the package does not use Intel's traditional EMIB architecture. Instead, Diamond Rapids employs UCIe-S interconnects carried over high-density copper traces in the package substrate, linking each of its four base tiles to two central Fabric Hub Tiles. The Fabric Hubs centralize key system functions, including memory controllers, I/O and coherency infrastructure.

Diamond Rapids Incorporates Robust Memory And I/O Complements For Agentic Workloads

Likewise, Intel significantly bolstered the platform’s memory subsystem to satisfy the data efficiency requirements of enterprise-scale agentic AI. Diamond Rapids expands memory support to a 16-channel architecture, capable of utilizing DDR5 memory up to 8,000MT/s as well as MRDIMMs reaching transfer rates of up to 12,800MT/s. The platform’s I/O fabric also delivers 128 lanes of PCIe Gen 6, CXL 3.0, and Ultra Path Interconnect 3.0 links.

Diamond Rapids also introduces native Advanced Vector Extensions 10.2 to support symmetrical 512-bit vector processing across performance and efficiency paradigms, alongside refreshed Advanced Matrix Extensions for native AI workload acceleration. Intel also debuted Advanced Performance Extensions, an instruction set that doubles general-purpose registers from 16 to 32, reducing memory load operations by 10% and store operations by 20% without requiring software developers to rewrite existing code bases.

Power management features integrated directly into the SoC help tame the energy demands of such a massive configuration. There's a core idle power state that retains L2 cache data while lowering power draw, priority-core turbo boosts for single-threaded bottlenecks, and specialized thermal management to dynamically balance power allocation between compute cores, high-speed memory, and external I/O channels.

Production for Diamond Rapids is slated to ramp toward a 2027 launch.