Intel Diamond Rapids Xeon 7 CPU Leaks With Massive 240MB L3 Cache
Operating conservatively at just 1.1 GHz in Intel's evaluation labs, this specific sample doesn't tell us much about the final performance of the parts, but it does offer a glimpse into a massively upscaled memory subsystem, as it sports 64 MB of L2 cache alongside a staggering 240 MB of L3 cache. Now, it's true that current-generation Granite Rapids chips max out at 288 MB across their highest configurations, but this part only has 32 cores, a quarter of those in the fastest Granite Rapids parts. It's possible that the fully unlocked 192-core variants of Diamond Rapids could field an unbelievable volume of L3 cache when they eventually deploy.
This engineering sample was tested on an Intel reference evaluation board codenamed "Johnson City," which is part of the broader Oakstream ecosystem. The Oakstream platform represents a massive topological upscale for Intel's server infrastructure, moving to a 16-channel DDR5 memory interface and native PCIe Gen 6 support while reportedly abandoning the 8-channel memory variants altogether. As we noted, these chips are made on Intel's 18A-P process node, a retuned iteration of the base 18A node that tweaks the voltage-frequency curve to supposedly deliver either a 9% performance uplift at iso-power or an 18% reduction in power consumption at matched performance. Crucially, the 18A-P node maintains full design-rule compatibility with the base 18A node, allowing Intel to efficiently reuse existing IP blocks and design flows while heavily scaling up its core counts.
Strategically, Diamond Rapids shifts Intel's data center focus squarely toward aggressive IPC and physical core count scaling by utilizing "Panther Cove-X" P-cores. Interestingly, the architectural layout of these cores is expected to closely mirror the consumer space, paving the way for the top-end Diamond Rapids SKUs to launch with up to 192 physical Panther Cove-X cores by mid-2027. Rumors even point to ultra-dense variants that could push boundaries up to 512 cores later in the product's deployment cycle, completely altering the density calculus for enterprise deployments.
One of the most consequential architectural shifts with Diamond Rapids is the complete removal of simultaneous multi-threading, or Hyper-Threading. By reducing scheduler complexity and shedding the power overhead associated with managing two logical threads per physical core, Intel is returning the ratio of physical cores to logical threads to a strict 1:1 ratio. While eliminating Hyper-Threading makes sense in the desktop and consumer space, where the presence of massive clusters of E-cores effortlessly handles background tasks and deeply threaded workloads without the need for SMT, the server ecosystem operates under vastly different market requirements. In data centers, heavy virtualization and high-throughput enterprise workloads thrive on maximized thread density, a metric where AMD's EPYC processors currently maintain a commanding lead.
That's likely why Intel has already concluded that stripping SMT from its Xeon lineup is a strategic misstep. During a recent earnings call, Intel CEO Lip-Bu Tan officially confirmed that the generation immediately following Diamond Rapids, codenamed Coral Rapids, will see the return of Hyper-Threading. Tan's confirmation that Hyper-Threading will be integrated into the 2028 Xeon 8 lineup heavily implies that enterprise customers pushed back on the thread-count deficit. Diamond Rapids will have to fight AMD's Zen 6 strictly on the merits of its physical core density and massive cache pools, and it will be fascinating to see how the three-way battle between Diamond Rapids, AMD's EPYC Venice, and NVIDIA's Vera ends up around the middle of next year.
Shout out to 188号 for the spot!
