AMD And JEDEC Are Collaborating On DDR5 MRDIMMs At A Blistering 17,600 MT/s

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Memory bandwidth isn't that big of a deal on desktop platforms. Client tasks like office work, web browsing, and even computer games are usually much more sensitive to memory latency than memory performance, which is why AMD sees such huge gains in gaming from its 3D V-Cache technology. Server and HPC tasks can be extremely thirsty for memory bandwidth, though—especially if they make use of wide SIMD instructions like AVX.

So, then, how to improve memory bandwidth? Well, you can clock them higher, but there are limits to signal integrity. Instead, you can add more memory channels to your CPU, but that drastically increases complexity of both the platform and the processor itself—not that that's stopping AMD or Intel from taking this route. Another way is to introduce a new memory standard that relaxes latencies to improves bandwidth just as we did with DDR2 thru the current DDR5.

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Intel's MCR-DIMM proposal is fundamentally similar to MRDIMMs.

Yet another way is to get clever and invent a new way to access the memory you already have. That's what both AMD and Intel already did—AMD with its HBDIMM proposal, and Intel with MCR-DIMMs. Thankfully, we're not going to see the industry diverge on this point, because JEDEC has worked with AMD to develop HBDIMM into a standard called MRDIMM. The MR stands for "Multi-Ranked Buffered DIMMs," and it is not entirely unlike RAID-ing your RAM.

MRDIMMs achieve double the data rate that the same hardware would offer in standard DDR5 mode by simultaneously accessing two memory ranks, whether on a single module or a pair of DIMMs. This is made possible by placing a mux between the memory and the CPU that combines the two 64-bit accesses into a single 128-bit data path for the CPU. Obviously, this buffering is going to add a bit of latency to the transfers, but JEDEC seems to believe that this will be offset by the higher transfer rate.

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Image: Robert Hormuth on LinkedIn, click to enlarge

The main benefit of this approach is that it has a minimal price premium; aside from the buffer/mux, MRDIMMs can be created from existing DDR5 memory stocks. Likewise, machines using MRDIMMs should in theory be backward compatible with standard DDR5 modules. A slide from a JEDEC presentation at Memcon in San Jose, posted by AMD's VP of Datacenter on LinkedIn, seems to imply that JEDEC expects MRDIMMs to start at 8800 MT/s and scale up to 17,600 MT/s by the third generation of the technology.

Interestingly, the slide also says that the need for DDR6 memory is "unclear" due to uncertainty about its value proposition. It goes on to say "Buffered only to deliver value?" possibly implying that MRDIMM technology could be the order of the day as system RAM moves forward. It's an interesting idea, but we wonder if the lower latency of standard DIMMs wouldn't be a better fit for typical client machines.