ASML, TSMC, And Samsung Team Up To Solve Next-Gen Chip Bottleneck

by Aaron Leong — Tuesday, September 08, 2026, 10:17 AM EDT

Workers stand next to an ASML EXE:5000 High NA EUV tool in Intel's Fab 25 in Oregon. — Workers next to an ASML EXE:5000 High NA EUV tool in Intel's Fab 25 in Oregon - Image: Intel

The semiconductor industry is entering a new phase as Samsung and TSMC commit to integrating ASML’s next-generation High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography into their manufacturing toolkits. To unleash the technology's full capability, these industry leaders are spearheading a joint shift toward larger, 12-inch photomasks.

For years, the extreme cost (estimated at upwards of $350 million per scanner) and unique engineering made chipmakers cautious about jumping straight into High NA EUV. However, the demand for advanced artificial intelligence hardware and shrinking transistor limits have forced their hand. Following early adoption by Intel, Samsung has announced plans to deploy ASML’s High NA EUV tools into high-volume manufacturing by 2028, targeting its advanced DRAM memory nodes to become the first memory maker to utilize the technology at scale. TSMC, the world’s largest contract foundry, also confirmed it will incorporate High NA EUV machines into its high-volume advanced node manufacturing starting in 2030, expecting the layers requiring the technology to rise significantly as AI chip architectures grow in complexity.

ASML Twinscan EXE:5200B used by Intel - Image: ASML

What makes High NA EUV technically challenging lies in its optical design. By raising the aperture from 0.33 to 0.55, the new systems deliver higher optical resolution to print finer circuit features. However, to prevent extreme light angles from distorting the pattern, ASML designed High NA EUV with anamorphic optics, thus shrinking the exposure field size on the wafer by half. Under the current, decades-old 6-inch photomask standard, large chips like AI accelerators cannot fit into a single exposure field. Engineers are therefore forced to split a single chip pattern across two separate 6-inch masks using a stitching process, which aligns the prints side-by-side. It's not the ideal solution as this technique creates manufacturing complexity, introduces potential alignment errors, and significantly lowers fab throughput.

To help transition the semiconductor field to 12-inch photomasks, TSMC and ASML (Advanced Semiconductor Materials Lithography) officially launched an industry-wide initiative, backed by Samsung through the Large Size Mask Consortium. According to the joint roadmap unveiled ahead of the SPIE BACUS conference in California, a functional 12-inch mask pilot line is expected to be functional by 2031, which will prepare 12-inch High NA lithography systems for full readiness in advanced volume production by 2033.