AMD Zen 7 Grimlock Reportedly Targets TSMC's Cutting-Edge 1.4nm A14 Process
Let's start with the big news: CTEE says that AMD's Zen 7 is slated for fabrication on TSMC's A14 process. As you could probably guess from the name, this is a 1.4nm-class or 14-angstrom-class lithography process. What's interesting is that, unlike Intel, who went all in on bleeding-edge manufacturing tech with its 18A process, TSMC's A14 process is not expected to have Super Power Rail, the company's backside power delivery technology. Intel's analog is PowerVia, which is present in its 18A process and found in shipping products like the Core Ultra 300 series CPUs (Panther Lake).
A Backside Power Delivery Network (BSPDN) is a huge trade-off. By moving power rails to the opposite side of the chip from data connections, you improve signal integrity, increase density, and allow for improved efficiency as a result. However, it also introduces thermal management problems since you can't just weld a heatsink to that side of the chip anymore. Furthermore, it horrifically increases manufacturing complexity and, as a knock-on effect, dumpsters your yields. Intel seems to be doing OK now on 18A, but it took a lot of tears, sweat, and cash to get there.
AMD may have looked at TSMC's predictions for its own back-side power delivery network technology, Super Power Rail, and said, "we'll pass for now." A14 is still expected to bring considerable density and efficiency improvements over the N2 process on which its Zen 6 processors are currently being fabricated as I write this. Also, moving to BSPDN requires radically re-thinking your chip's entire design, and AMD may simply not have the resources available to make that kind of commitment just yet, especially considering that we don't know how well TSMC's Super Power Rail is going to work.
The other bit of news out of the CTEE report was that AMD's CEO Dr. Lisa Su personally visited the facilities of Taiwan's Powertech Technology Inc to check out the company's site ahead of signing with the company with the intent to use its FOPLP (Fan-Out Panel-Level Packaging) for upcoming processors. It's not clear necessarily which processors these would be, but based on what the technology is, it seems likely that it could be used for future consumer chips, or possibly GPUs.
Essentially, FOPLP is an alternative to TSMC's CoWoS chip assembly technology. Because of the insatiable demand for AI chips (especially competitor NVIDIA's AI chips), TSMC's CoWoS has become a major bottleneck in processor production. If AMD can partner with Powertech to use that firm's assembly services instead, it could alleviate a major supply bottleneck in the company's production pipeline.
As for Zen 7 itself, well, Zen 6 is thought to be primarily a platform upgrade, with relatively few changes to the inside of the CPU core versus Zen 5 aside from support for some new AI acceleration instructions. Zen 7, on the other hand, is said to double the amount of L2 cache per core, add support for AVX10 and the new AI Compute Extensions (ACE) proposed by the x86 Ecosystem Advisory Group, and radically increase IPC over Zen 6. Infamous leaksman Tom at Moore's Law is Dead claimed the uplift could be as high as 25% over Zen 6, which would be titanic.
Unfortunately, we won't be seeing Zen 7 chips until late 2028 at the absolute earliest, and even Zen 6 chips are still half a year away. At least we can take some comfort in the fact that Zen 7 is widely expected to come to Socket AM5 as the final architectural send-off for those systems. Both AMD and Intel are expected to move consumer platforms to DDR6 memory in 2029 or 2030.
