An Introduction To AMD Spin-Off Global Foundries

As we've mentioned, Fab 2 will be a leading-edge facility in and of itself. But to staff and run the fab, and to ensure its success and ability to innovate over time, Global Foundries will be relying on its existing partnerships and nearby colleges and universities.

Global Foundries is already part of a collaborative alliances with companies like IBM, ST, Chartered, Samsung, Toshiba, and others. With the knowledge gained through the alliances and with research taking place at the College of Nanoscale Science and Engineering, however, Global Foundries intends to not only build Fab 2, get it online, and woo potential customers, but to pioneer significant innovation along the way, not just be a workhorse facility.

   

   

   
Fab Process Capabilities

Some of Global Foundries' current capabilities and a few of the breakthroughs that have already been achieved by some of their partners are presented in the slides above. They were already first to market with an Immersion Lithography process, which decreases the wavelength of lithography by putting water between the projection lens and silicon wafer, and they plan to convert part of Fab 1 to use Immersion Lithography sometime in the middle of this year. 32nm SOI silicon is already running in Fab 1 as well and tape-outs will be accepted in late 2009 with an early 2010 production ramp planned for 32nm bulk manufacturing.

Some of the innovations planned with the high-performance 32nm SOI process include a High-k / Metal Gate “Gate First” transistor design approach that reportedly minimizes complexity and cost, while also lowering capacitance for lower power and improved performance. An Ultra-Low-K dielectric, which introduces air-filled pores throughout the insulator, is also planned, as is a 28nm low-power bulk CMOS process. Next generation technologies that are also planned by Global Foundries and its partners also include module structures and processes like 3D ICs, Multi-gate FinFETs which represent a new transistor structure, and EUV, or Extreme Ultra Violet Lithography. The first field tested chips created using EUV have already been demonstrated, although the technology is likely needed for 15nm and beyond.