PCI Express 7 Draft Spec Targets Glorious 512GB/s Of Bandwidth For Next Gen Devices
There's no big surprises in the next-generation interconnect's new specification, at least at the surface level. Historically, new PCIe revisions double per-lane bandwidth, and that is indeed the case here: PCIe 7.0 increases the per-lane peak transfer rate from 8GB/second on PCIe 6.0 up to 16GB/second.
Note: This table shows bidirectional bandwidth per lane
Of course, both are much faster than the PCIe 4.0 and 5.0 connections available in current-generation systems, which run at 2GB/sec and 4GB/sec per direction per lane, respectively. Even those transfer rates are astonishing when you start piling up the lanes; a typical PCIe 5.0 M.2 socket has some 16 gigabytes per second of full duplex bandwidth. An equivalent PCIe 7.0 device would theoretically support up to 64GB/second transfers.
PCIe 6.0 achieved its transfer rate increase by switching to PAM4 signaling, which is also used in 400-Gigabit Ethernet and GDDR6X memory. PAM4 signaling encodes more information at the same transfer rate, which means very high signal integrity is required, but it allowed PCI-SIG to avoid raising the physical clock speed.
PCIe 7.0, in contrast, still uses PAM4 signaling, but now doubles the clock rate once again. This is going to make some serious manufacturing challenges for companies building PCIe 7.0 hardware, as they need to maintain extremely clean signaling at ludicrously-high clock rates to make a good PCIe 7.0 connection.
You might wonder why even bother with such speeds at this time. After all, the difference between PCIe 4.0 and PCIe 5.0 for graphics cards is basically nil, and even storage struggles to max out a PCIe 5.0 interface. That obviously won't be the case forever, but moreover, there are already use-cases for faster interconnects in large servers and the high-performance computing arena.
Besides extremely-high-speed networking and massive storage arrays, there are also products like Compute Express Link (CXL) that rely on the PCIe physical layer to do their thing. CXL aims to be, among other things, an interface for storage-class memory, and memory interfaces are usually a lot faster than current-gen PCIe.
The current publication is PCIe 7.0 draft version 0.3, and the specification is available to members of PCI-SIG. If you're of a mind to read the specification, you'll have to be a member, or get it form someone who is. For the rest of us, well—PCI-SIG probably won't publish the final PCIe 7.0 specification until 2025, and we likely won't see hardware with the interconnect until 2027 or later.
