Intel sends more details tonight of something we learned a bit about at this past Fall IDF. We have specific details of the architecture that comprises Intel's mysterious Teraflop 80-Core processor. This breakthrough comes in the form of a dedicated function circuit but its design and implementation show promise for highly scalable SoC and NoC architectures in the future, with leading edge processes like those that are being developed at Intel's Hillsboro, Oregon facility.
The PE (processing engine) contains two independent fully-pipelined single- precision floating-point multiply-accumulator (FPMAC) units, 3KB single-cycle instruction memory (IMEM), and 2KB data memory (DMEM). A 96-bit VLIW encodes up to eight operations per cycle. With a 10-port (6-read, 4-write) register file, the architecture allows scheduling to both FPMACs, simultaneous DMEM load and stores, packet send/receive from mesh network, program control, and dynamic sleep instructions. A router interface block (RIB) handles packet encapsulation between the PE and router. The fully symmetric architecture allows any PE to send (receive) instruction and data packets to (from) any other tile."
Whenever they use words like "mesochronous" you know they ain't messin' around. The engine core router approach is probably one of the most impressive aspects of this architecture. That and the fact that they've squeezed 80 of these subsystems on a single chip. Download Intel's PDF on the tech, right here.