Intel's Pentium D Exposed A Chiplet Challenge That's Still Relevant Today
How's your Throwback Thursday going? As it happens, we've got a perfect post for you today, thanks to former Intel Performance Architect François Piednoel. Posting on LinkedIn, Piednoel shared an anecdote about his days at Intel as part of a blog entry called "Chiplet, not so fast, did you look at everything?" that highlights one of the major challenges chipmakers face when creating chiplet-based processors.
François Piednoel was an important figure at Intel who was responsible for performance analysis and optimization. His crowning achievement, by his own telling, was introducing the roadmap for moving Intel away from the disappointing NetBurst architecture introduced with the Pentium 4 toward the Core series, which was itself derived from the older P6 core that powered the Pentium Pro, Pentium II, and Pentium III. Before that, though, he worked on the Pentium 4 and its descendants as they were the company's main offerings.
In the LinkedIn post, Piednoel talks about the challenges the company faced creating "multi-chip packages" for the Pentium D family. Back in those days, the CPU was essentially what we would now call a single "core", as all of the I/O was handled off-chip, even memory. Given that, it was actually relatively straightforward to build a dual-core processor by simply sticking two processor dies in the same package, wired up to the same bus. Not easy, necessarily, but as the man himself states, the path to the part was direct thanks to the bus having already been designed around symmetric multi-processing from the get-go.
The problem that Piednoel's team ran into was apparently not one of function but of reliability. The former Intel man describes that a significant portion of Pentium D packages "began failing unexpectedly, and surprisingly early in the validation cycle." This was happening despite that the CPUs being paired were parts from the exact same performance bin.
As it happened, the issue turned out to be that -- while the team had matched frequency -- they hadn't matched leakage current, and the increased power draw of having two in the same socket led to a thermal runaway situation if one of the chips had sufficiently higher leakage than the other. Once Intel started matching the chips based on leakage as well as frequency, the failures disappeared. The "Smithfield" Pentium D would go on to be Intel's first dual-core processors, and while they were relatively hot and power-thirsty, they did offer a real performance uplift over the previous-gen Pentium 4 HT processors.
After telling this story, he pivots his post to talk about modern processors, explaining that chiplet-based SoC design (particularly when featuring heterogeneous chiplets) requires a tremendous amount of extra testing and validation. "The complete assembly must still be characterized as a coupled electrical and thermal system not simply as a collection of individually qualified dies," he notes. It's for this reason that his own "chiptile" design focuses on using identical chiplets rather than heterogeneous chiplets, as it's much easier to scale that way since it requires less work in validation.
Still, it's obvious that AMD, Intel, NVIDIA, TSMC, ASE, Amkor, and all of the other companies involved in multi-die processor packaging and fabrication are intimately familiar with the extra work involved in moving to chiplets. There are certainly trade-offs, as NVIDIA correctly emphasized in its Vera CPU marketing (even as it ships chiplet-based Rubin GPUs right alongside.) It's just that the benefits in terms of scalability and manufacturing economics seem to justify the extra cost and difficulty; if they didn't, we wouldn't see nearly every major chip vendor moving to disaggregated designs with fully heterogeneous processors.
