IBM Just Shattered Moore's Law With Sub-1 Nanometer Chips
According to IBM, the new technology can pack nearly 100 billion transistors onto a chip roughly the size of a fingernail. It's nearly double the density of the company's prior 2nm research chip announced in 2021 and currently being commercialized by Rapidus in Japan. IBM projects the design could deliver up to 50% higher performance or 70% greater energy efficiency compared to its earlier 2nm technology.
Now, before anyone imagines transistors literally measuring less than a nanometer across, it's worth noting that modern process node names no longer correspond directly to a specific physical dimension. Today's "2nm," "3nm," and "5nm" technologies are better understood as generations or "classes" of manufacturing technology than exact measurements.
Still, IBM's work appears to represent a genuine advance. The company's new Nanostack architecture builds on today's leading-edge gate-all-around (GAA) nanosheet transistors, such as Intel's RibbonFET technology used in its 18A process. Rather than relying solely on shrinking features in two dimensions, IBM says Nanostack vertically stacks and staggers transistor structures using a three-dimensional integration technique, potentially allowing engineers to continue increasing transistor density by building upward.
The concept bears some resemblance to Complementary FET (CFET) designs that have been proposed across the semiconductor industry as a successor to today's nanosheet transistors. CFET architectures stack NMOS and PMOS transistors vertically to reduce footprint and improve density. Based on IBM's description, Nanostack may represent an evolution of those ideas, although the company hasn't yet publicly disclosed enough technical detail to fully compare its approach against existing CFET research.
That approach may become increasingly important as semiconductor manufacturers run into the realities of atomic-scale engineering. IBM notes that certain critical dimensions are now approaching the scale of individual atoms, making further conventional scaling increasingly difficult. The company also claims Nanostack enables different material combinations within stacked transistor layers, potentially allowing engineers to optimize individual layers for performance, power efficiency, or other characteristics independently. If those capabilities prove practical in manufacturing, such flexibility could be valuable for a vendor trying to fabricate chips for diverse design targets on the same process.
Perhaps most importantly, IBM says the technology has moved beyond theoretical modeling. Researchers demonstrated functional CMOS inverter operation, indicating that the architecture can perform real computation rather than existing solely as a laboratory concept. IBM also reported SRAM scaling improvements of roughly 40%, a noteworthy development given the growing importance of memory density and bandwidth in modern AI workloads. SRAM is used for processor cache, and IBM says the result represents the largest SRAM scaling improvement seen in roughly a decade.
As with many semiconductor research breakthroughs, commercialization remains the biggest question. The industry, and in particular IBM, has a long history of promising technologies that proved difficult or uneconomical to manufacture at scale. However, IBM believes nanostack technology could enter production within the next five years. If IBM's manufacturing projections prove accurate, the breakthrough may ultimately be remembered less for introducing a "0.7nm" node and more for accelerating the semiconductor industry's transition toward increasingly three-dimensional transistor designs. Rather than endlessly shrinking transistors, the future of chip development may depend on stacking them.
