Intel Expects Strong Demand For Sandy Bridge; Hints at Early Launch
One other additional tidbit of information from Intel's recent conference call offers some tantalizing rumors about the upcoming Core i7 architecture, codenamed Sandy Bridge. Officially, Intel isn't expected to launch SB until the end of Q4, but the chip is ramping well enough that Santa Clara might opt to pull the launch forward slightly and ship for revenue earlier.
For those of you who aren't up on Intel's latest codenames, Sandy Bridge is a "tock" in Intel's Tick-Tock model. Intel splits its processor releases along these lines; a 'tick' refers to the launch of a new process technology, a 'tock' is a new CPU design. In this case, Intel isn't focusing on clock speeds (early projections have Sandy Bridge shipping at 2.8 - 3.4GHz w/out Turbo Boost), but on increased execution and power efficiency. The CPU's major new feature that addresses both concerns is its support for AVX (Advanced Vector Extensions). Think of AVX as a standard SIMD instruction set pumped full of monster-creating radiation and Vitamin X. Intel is predicting that a CPU that makes full use of AVX instructions could be up to 4x faster double-precision FPU workloads compared to traditional x87 code. Even if we toss that number out as a theoretical maximum, AVX could still easily deliver a sizeable boost to FPU performance.
Other changes include the fact that Sandy Bridge-derived CPUs will include the GPU on-die (as opposed to on-package as with the current lineup of Clarkdale/Arrandale processors). Cache sizes will stay the same (256K L2 / 8MB L3) but in this case, the L3 cache will actually be shared with the integrated
GPU. How much of a performance boost we can expect from this is unclear—even if the GPU had priority over the L3 cache, 8MB of L3 makes for an awfully slow frame buffer. It's also possible that Intel will introduce other improvements that deal with the CPU's ability to pass data between its various cores. Intel isn't talking much about its plans at this point, but it's possible the CPU manufacturer will launch Sandy Bridge a bit early to take the wind squarely out of AMD's Llano. Unlike Nehalem, which first launched at the high end of the midrange and then graduated to lower price segments very slowly, Sandy Bridge should hit multiple price points as soon as it drops. With Llano, AMD is targeting both high frequency and low power consumption; Intel's SB architecture could make it even harder for Sunnyvale to hit its performance goals—as if existing Clarkdale/Arrandale processors weren't tough enough to beat.
We expect AMD's Llano will target relatively high frequencies on both GPU and CPU (while maintaining reasonable performance). Since Llano is designed to be flexible (2-4 cores on-die, in addition to the GPU), it's logical to think Sunnyvale will continue its tactic of challenging Intel's superior IPC (instructions per clock cycle) with additional cores. This philosophy has paid off fairly well for the Phenom II X6 product series; a lineup of quad-core Llano parts at 3GHz priced against Intel's dual-core chips could keep AMD squarely in the game even if it doesn't put the CPU manufacturer over the top.
For those of you who aren't up on Intel's latest codenames, Sandy Bridge is a "tock" in Intel's Tick-Tock model. Intel splits its processor releases along these lines; a 'tick' refers to the launch of a new process technology, a 'tock' is a new CPU design. In this case, Intel isn't focusing on clock speeds (early projections have Sandy Bridge shipping at 2.8 - 3.4GHz w/out Turbo Boost), but on increased execution and power efficiency. The CPU's major new feature that addresses both concerns is its support for AVX (Advanced Vector Extensions). Think of AVX as a standard SIMD instruction set pumped full of monster-creating radiation and Vitamin X. Intel is predicting that a CPU that makes full use of AVX instructions could be up to 4x faster double-precision FPU workloads compared to traditional x87 code. Even if we toss that number out as a theoretical maximum, AVX could still easily deliver a sizeable boost to FPU performance.
Other changes include the fact that Sandy Bridge-derived CPUs will include the GPU on-die (as opposed to on-package as with the current lineup of Clarkdale/Arrandale processors). Cache sizes will stay the same (256K L2 / 8MB L3) but in this case, the L3 cache will actually be shared with the integrated
GPU. How much of a performance boost we can expect from this is unclear—even if the GPU had priority over the L3 cache, 8MB of L3 makes for an awfully slow frame buffer. It's also possible that Intel will introduce other improvements that deal with the CPU's ability to pass data between its various cores. Intel isn't talking much about its plans at this point, but it's possible the CPU manufacturer will launch Sandy Bridge a bit early to take the wind squarely out of AMD's Llano. Unlike Nehalem, which first launched at the high end of the midrange and then graduated to lower price segments very slowly, Sandy Bridge should hit multiple price points as soon as it drops. With Llano, AMD is targeting both high frequency and low power consumption; Intel's SB architecture could make it even harder for Sunnyvale to hit its performance goals—as if existing Clarkdale/Arrandale processors weren't tough enough to beat.
We expect AMD's Llano will target relatively high frequencies on both GPU and CPU (while maintaining reasonable performance). Since Llano is designed to be flexible (2-4 cores on-die, in addition to the GPU), it's logical to think Sunnyvale will continue its tactic of challenging Intel's superior IPC (instructions per clock cycle) with additional cores. This philosophy has paid off fairly well for the Phenom II X6 product series; a lineup of quad-core Llano parts at 3GHz priced against Intel's dual-core chips could keep AMD squarely in the game even if it doesn't put the CPU manufacturer over the top.
