IBM Chips: A River Runs Through It

Researchers at IBM's Zurich Research Laboratory have developed a new technique that gives a whole new meaning to water cooling: Circulating water inside the chip itself. The concept is not meant for today's CPUs, but actually for the chips of tomorrow. 

Historically, CPU performance improvements have largely been a function of generating faster computational speeds. But higher speeds require smaller manufacturing processes and generate more heat--thus trying to eke out more MHz from CPU design advances becomes increasingly difficult and less efficient. This is one of the reasons why CPU manufacturers have switched their performance focus from more MHz to multi-core processors.

But more cores means larger chips, which presents manufacturing challenges. Even as manufacturing processes continue to get smaller and more efficient, those advances can be all but wiped out as the chips need increase in physical size to accommodate the additional cores.

The solution to this problem is to start thinking in three dimensions. The next evolutionary step in chip design is likely to be "3-D chip stacks," where processor and memory layers are physically stacked on top of each other, instead of laid out "side-by-side." A key benefit to this concept is that it significantly improves the efficiency of chip interconnects:

"[It] drastically shortens the distance that information needs to travel on a chip to just 1/1000th of that on 2-D chips and allows the addition of up to 100 times more channels, or pathways, for that information to flow."

One problem solved, but another one created. IBM's Zurich Research Laboratory, project leader, Thomas Brunschwiler, explains: "As we package chips on top of each other to significantly speed a processor's capability to process data, we have found that conventional coolers attached to the back of a chip don't scale. In order to exploit the potential of high-performance 3-D chip stacking, we need interlayer cooling."

And interlayer cooling is exactly what scientists at IBM's Zurich Labs have recently demonstrated with a working prototype:

"In these experiments, scientists piped water through a 1 by 1 cm test vehicle, consisting of a cooling layer between two dies or heat sources. The cooling layer measures only about 100 microns in height and is packed with 10,000 vertical interconnects per cm2. The team overcame key technical challenges in designing a system that maximizes the water flow through the layers, yet hermetically seals the interconnects to prevent water from causing electrical shorts. The complexity of such a system resembles that of a human brain, wherein millions of nerves and neurons for signal transmissions are intermixed but do not interfere with tens of thousands of blood vessels for cooling and energy supply, all within the same volume."

"The fabrication of the individual layers was accomplished with existing 3-D packaging fabrication methods to etch or drill the holes for signal transmission from one layer to the next. To insulate these "nerves", scientists left a silicon wall around each interconnect (also called through silicon vias) and added a fine layer of silicon oxide to insulate the electrical interconnects from the water. The structures had to be fabricated to an accuracy of 10 microns, 10 times more accurate than for interconnects and metallizations in current chips."

With this major hurdle now apparently overcome, the next evolutionary step in chip design is ready to step up--literally.
Tags:  IBM, Chip, chips, IPS, Ive, IP