AMD EPYC Zen 4 Genoa CPUs Rumored With Up To 96 Cores And 12-Channel DDR5 Memory

AMD's next round of server processors are going to be EPYC beasts, if recently leaked documents end up being legitimate. These supposedly official documents outline some of the characteristics of AMD's next-gen EPYC processors based on its upcoming Zen 4 architecture, including the SP5 socket design they will slip into, and the possible max core count.

As things currently stand, AMD's EPYC 7003 series based on Zen 3 (codenamed Milan) scale to 64 cores and 128 threads of raw compute muscle. That is the core and thread configuration found on the company's EPYC 7713/7713P and 7763 processors, with boost clocks maxing out at 3.675GHz for the former and 3.5GHz for the latter.

Looking ahead to AMD's next-gen EPYC stack based on Zen 4, codenamed Genoa, past rumors suggested we are looking at up to 128 cores and 256 threads. And that indeed appears to be the case, based on some documents hackers stole from Gigabyte during a recent ransomware attack, and have now published to the web.
Prominent leaker Yuko Yoshida waded through the leaked documents and posted a series of screenshots to Twitter. In one of them, we see an EPYC diagram with a larger I/O die flanked by a series of core complex dies (CCDs), as is the case with both Rome and Milan. However, the documents suggest AMD has bumped up the number of CCDs from eight to 12.

Previously, each of the eight CCDs contained up to eight cores, for a total of 64 cores (and 128 threads). But with the upcoming EPYC processors being armed with a dozen CCDs, that paves the way for a 96-core/128-thread configuration, as has been previously rumored.

The leaked documents also seemingly confirm support for 12-channel DDR5 memory, and offer up some details about power consumption and the SP5 socket, which features 6,096 pins in a Land Grid Array (LGA) format, making it AMD's biggest socket to date.
According to the documents, AMD managed to shrink the CCD from 80mm (Zen 3) to 72mm (Zen 4), which is around an 11 percent reduction. AMD also took a shrink ray to the I/O die—in measures 397mm in Genoa, down from 416mm. The entire package measures 5,428mm2, with the SP5 socket checking in at 6,080mm2 (SP3 measures 4,410mm2).

Finally, let's talk power requirements. One of the documents claims the peak power of the SP5 socket will be 700W, for very short bursts (just 1 millisecond). Peak power for 10-millisecond bursts is said to be 440W, and the peak power with PCC checks in at 600W.

"The processor may draw more than TDC for brief, non-thermally-significant durations," the document explains. "Peak power describes the processor's response and recovery time from such an event across all power supply rails. When instantaneous power exceeds the cTDP or package power limit, the processor returns thse limits with 30ms."

None of this comes as a huge surprise. We already know Zen 4 is in the pipeline, and that it will support DDR5 memory. We could also have anticipated a new socket for the server line, even without past rumors and leaks (AMD already confirmed there will be a new socket for consumers). Still, it's interesting to browse through some of the white paper details ahead of launch, which will take place sometime next year.