AMD EPYC Zen 3 Milan CPUs Get New L3 Cache Design, Zen 4 Genoa Adds SP5 Socket, DDR5

AMD is riding high on its Zen 2 CPU architecture, both on the desktop and in the server sector, and has managed to steal some market share from Intel because of its recent success. Lest anyone think AMD will now rest on its laurels, the company put that notion to rest during a recent HPC-AI Advisory Council conference in the UK. It was there that AMD revealed some interesting details about its future plans for its EPYC server chips.

Zen 3 EPYC CPUs (codenamed "Milan") loom in the distance, and further out sits Zen 4 EPYC silicon (codenamed "Genoa"). It may feel a bit early to discuss server processors that are up to two generations away, given that AMD is currently scoring wins with its Zen 2 "Rome" EPYC processors, but the wheels of tech never stop spinning.

AMD EPYC Zen 3 Milan And Zen 4 Genoa CPU Roadmap

AMD EPYC Roadmap

A look at the roadmap slide shows that AMD's Zen 3 Milan EPYC processors have already reached the tapeout stage, meaning the initial design is complete, and will go into production for a customer launch in 2020. It also appears AMD is targeting 2020 for the tapeout of its Zen 4 Genoa EPYC processors, followed by a launch in 2021, if all goes to plan.

The slide reiterates what we already know about the Zen 3 architecture, which is that it is based on an enhanced 7-nanometer node, dubbed 7nm+. It is the same underlying architecture that will be found in AMD's next-generation Ryzen 4000 series CPUs for desktop consumers.

AMD Zen 3 Milan EPYC Socket And Cache

Milan will retain socket compatibility with current SP3 platforms. What that essentially means is another round of DDR4 memory support and many of the same features, with the bulk of changes coming from the architectural enhancements—AMD is taking aim at more performance per watt, as would be expected with a new generation of processors.

AMD did not share any details about clockspeeds, and it will be interesting to see how that shakes out. In an interview with EETimes last year, AMD CTO Mark Papermaster noted "Moore's Law is slowing down, semiconductor nodes are more expensive, and we're not getting the frequency lift we used to get."


While AMD did not share information about clockspeeds, it did discuss a change to the cache makeup. Zen 3 will bring about a change compared to Zen 2—whereas Zen 2 features 16MB of L3 cache per core complex (CCX) within a core complex die (CCD), Zen 3 will have a shared cache design consisting of 32MB or more of L3 cache for each CCD.

This alteration means each core would share the whole lot of L3 cache, rather than have access to just a portion of the overall allotment. It will be interesting to see what effect this ends up having on performance.

What We Know About AMD's Zen 4 EPYC Genoa Processors

We will have our answers about Milan's performance soon enough. Looking further down the roadmap, however, Zen 4 will bring about some more changes to the EPYC ecosystem. To start with, Zen 4 EPYC Genoa processors will feature a new SP5 socket. That means Milan will be the end of the road for the current SP3 platform.

Genoa processors will also introduce support for DDR5 memory. This suggest that DDR5 will also permeate the consumer desktop with Zen 4-based Ryzen and Threadripper CPUs.

AMD also apparently indicated that Genoa will bring about new capabilities. What those are remains to be seen, but support for the PCI Express 5.0 specification is certainly on the table. PCIe 5.0 doubles the bandwidth of PCIe 4.0, which could pay dividends in the server sector.

Summed up, AMD has built up some momentum with its Zen architecture and appears to be in good shape going forward.