AMD Announces SSE5 Instruction Set

by Marco Chiappetta — Thursday, August 30, 2007, 12:30 PM EDT

AMD to Boost Performance for Everyday Compute-Intense Multimedia, Security and High Performance Computing Applications through New Extensions to x86 Instruction Set

New instruction set “SSE5” continues tradition of AMD x86 innovation, including 3DNow!, AMD x86-64 architecture, AMD Virtualization and Light-Weight Profiling specification

SUNNYVALE, Calif -- August 30, 2007 --AMD today announced further plans to innovate the x86 architecture by introducing SSE5, a new extension of the x86 instruction set that is designed to allow software developers to simplify code and achieve greater efficiency for the most performance-hungry applications. SSE5 will give developers additional capabilities to help maximize the performance of applications that have daily impact on consumers and enterprises, including high performance computing, multimedia and security applications. By making the SSE5 specification available to developers today, AMD expects to ease the adoption of the new instructions for tool providers and software vendors who develop these performance-intense applications.

“Chip advancements and software improvements go hand-in-hand, to the benefit of consumers and enterprises alike,” said Phil Hester, senior vice president and chief technology officer, AMD. “The impact of our designs are best realized when AMD-based servers, PCs and devices enable software to more effectively solve every-day problems and enhance every-day experiences. By announcing our plans to add SSE5 instructions to the x86 instruction set ? and by making the specification available today ? we are enabling open and collaborative software innovation that will bring AMD’s advancements to life for our customers and end-users.”

As the industry’s focus is shifting from processor speeds to increasing power efficiency, the number of instructions executed per second on one processor core remains relatively constant. As a result, both software and hardware vendors must pursue new approaches to improving computing performance...

Tags: AMD, CES, SSE5, SSE, E5, AM

Marco Chiappetta

Marco's interest in computing and technology dates all the way back to his early childhood. Even before being exposed to the Commodore P.E.T. and later the Commodore 64 in the early ‘80s, he was interested in electricity and electronics, and he still has the modded AFX cars and shop-worn soldering irons to prove it. Once he got his hands on his own Commodore 64, however, computing became Marco's passion. Throughout his academic and professional lives, Marco has worked with virtually every major platform from the TRS-80 and Amiga, to today's high end, multi-core servers. Over the years, he has worked in many fields related to technology and computing, including system design, assembly and sales, professional quality assurance testing, and technical writing. In addition to being the Managing Editor here at HotHardware for close to 15 years, Marco is also a freelance writer whose work has been published in a number of PC and technology related print publications and he is a regular fixture on HotHardware’s own Two and a Half Geeks webcast. - Contact: marco(at)hothardware(dot)com