Potentially Beastly Apple M1 Quadra CPU Detailed In Chip Die Map Analysis

Illustration of possible die-to-die interconnect on M1 Max
It seems Apple may have a secret trick up its sleeve regarding the future of its M1 System on a Chip (SoC). A detailed analysis of the M1 Max silicon shows the architecture may have a previously undiscovered interconnect bus. This would allow the Cupertino-based company to stack multiple dies together to greatly increase the number of CPU and GPU cores. The technology, known as Multi-Chip-Module (MCM) scaling, allows the manufacturer to stack multiple dies together in a chiplet-based design. In theory, Apple could easily scale the M1 Max to have as many as 40 CPU cores and 128 GPU cores. System memory would also greatly increase, doubling or quadrupling.

Potentially Beastly Apple M1 Ultra Detailed n Chip Die Map Analysis
Apple, M1, M1 Pro And M1 Max CPU Die

Twitter user @VadimYuryev showed the hidden section on the bottom of an M1 Max chip (seen above in our hero shot). It’s important to note, this potential interconnect was never included in Apple’s official renders of the M1 Max die.

Connecting multiple M1 Max chips together in this manner would result in essentially an M1 Max Duo or even an M1 Max Quadra. Other analysts have been suggesting this possibility for months Now. In May 2021, programmer and tech writer John Siracusa suggested Jade-C as the building block for Pro Mac SoCs.

Depiction of Jade-C chip design suggested by John Siracusa
Image Credit: John Siracusa

In his illustration, Siracusa shows a slimmed-down version of the M1, sacrificing 16 GPU cores for a smaller size factor. He also depicts 2C and 4C dies, joining together two and four M1 SoCs respectively into a single package.

Siracusa's Jade-C design suggestion, showing a 4-die SoC
Siracusa's illustration of the Jade-4C design concept
In another depiction, Frederic Orange shows the M1 Max Duo as a multi-die MCM, with the M1 Ultra using chiplet design. Since the interconnect bus only exists on one side of the silicon, the M1 Max Quadra would likely require an I/O die joining two interconnected pairs of SoCs.

Comparison of actual M1 Max with Apple image
Image Credit: Frederic Orange

Apple's M1 Pro chip, an intermediate SoC between the M1 and M1 Max in terms of performance, doesn’t have the interconnect bus. This probably means Apple intends the performance scaling only for users who need it, like 3D rendering or video production workstation pros. The M1 Pro and Max already outperform most Intel processors; joining two or four of them together would definitely up the ante.