Intel Shows Off 10nm Cannon Lake Wafer For Next Generation Core Processors

Intel Cannon Lake Wafer

We are getting closer to the launch of Cannon Lake, the highly anticipated processor architecture that Intel has been working on for what feels like an eternity. There is still no exact release date for Cannon Lake, though Intel did whip out a wafer of the forthcoming architecture at its Technology and Manufacturing Day held in Beijing, China. The message? Moore's Law is alive and well.

Cannon Lake represents a major feat in engineering, as it will be the first processor architecture from Intel to be built on a 10-nanometer manufacturing process. Current generation Kaby Lake and even Coffee Lake, which has not yet released to desktop but is available in mobile form, are both built on a 14nm manufacturing process. The 14nm node was introduced by Skylake a little over two years ago. Prior to that, Intel was building processors on a 22nm process (dating back to Ivy Bridge).

"Intel manufacturing processes advance according to Moore’s Law, delivering ever more functionality and performance, improved energy efficiency and lower cost-per-transistor with each generation," said Stacy Smith, group president of Manufacturing, Operations and Sales. "We are pleased to share in China for the first time important milestones in our process technology roadmap that demonstrate the continued benefits of driving down the Moore’s Law curve."

Intel is not the first semiconductor to build a 10nm chip—MediaTek, Qualcomm, and Samsung each have mobile processors built on a 10nm FinFET manufacturing process. However, Intel is quick to point out that its 10nm technology is more advanced than all other 10nm technologies and a "full generation ahead," both in terms of transistor density and transistor performance.

To make clear how advanced Intel's 10nm technology is compared to the competition, Intel Senior Fellow Mark Bohr proposed a standardized density metric to show where manufacturing processes stand in relation to Moore's Law.

Intel Transistor Density
Source: Intel (Click to Enlarge)

"Moore’s Law, as stated by our co-founder over half a century ago, refers to a doubling of transistors on a chip with each process generation. Historically, the industry has been following this law, and has named each successive process node approximately 0.7 times smaller than the previous one—a linear scaling that implies a doubling of density. Thus, there was 90 nm, 65 nm, 45 nm, 32 nm— each enabling the packing of twice the number of transistors in a given area than was possible with the previous node," Bohr explains.

"But recently—perhaps because of the increasing difficulty of further scaling—some companies have abandoned this rule, yet continued to advance node names, even in cases where there was minimal or no density increase. The result is that node names have become a poor indicator of where a process stands on the Moore’s Law curve," Bohr added.

Bohr says one measurement is gate pitch (a measurement of gate width plus spacing between transistor gates) multiplied by minimum metal pitch (interconnect line width plus space between lines). However, this does not take into account logic cell design. Another of his ideas is to use a metric based on gate pitch multiplied by logic cell height, which he says is a step in the right direction.

In any event, Cannon Lake is an advanced architecture, one that can't arrive fast enough.