Analysis Says Intel 10nm Process Enables 2.7X Density Over 14nm INTC Nodes
It seems as though we have been waiting an eternity for Cannon Lake to arrive in volume, and barring any further delays, it will be here in mass quantities next year. In the meantime, Intel has already released a 10-nanometer processor in mobile form, that being the Core i3-8121U, giving us a glimpse of Cannon Lake. It also gives us an opportunity to dissect the architecture a tad and see what Intel's 10nm process brings to the table.
In case you missed it, the Core i3-8121U made its first appearance last month inside Lenovo's IdeaPad 330 ultraportable laptop. The CPU is also listed on Intel's website, so it is not as though Intel is hiding its first 10nm consumer chip. It is a dual-core processor that supports Hyper Threading (2 cores and 4 threads, in other words), running at a base clockspeed of 2.2GHz with a max turbo clock of 3.2GHz. It also has 4MB of SmartCache (L3 cache) and a 15W TDP.
What it doesn't have are any integrated graphics. This has led to speculation that Intel is having trouble shrinking its graphics architecture down to 10nm and is one of the reasons why volume production of Cannon Lake keeps getting pushed further down the track, though nothing along those lines has been substantiated. Whatever the case might be, the Core i3-8121U provides some interesting details about Intel's 10nm process node.
TechInsights, a technology company that bills itself as a strategic patent and technology firm specializing in advanced reverse engineering services, published a paper that provides a brief analysis of Cannon Lake, based on the aforementioned chip. It's more of a recap, really, but interesting nonetheless. According to the paper, Cannon Lake in its current mobile form has a transistor density of 100.8 mega transistors for mm2. This represents a 2.7X increase in density over the company's 14nm node.
The paper also states that Cannon Lake is built on a third-generation FinFET process. Using this process, Intel was able to shrink the minimum gate pitch from 70nm to 54nm, and the metal pitch from 52nm to 36nm.
None of this is brand new information. Intel revealed some details about its 10nm node last year, at which time it made the claim that its 10nm node pushes a 2.7X increase in transistor density over 14nm. Intel has also held firm that it's manufacturing processes are more advanced than the competition, and even went as far as saying that node names are a poor indicator of where a process node stands on the Moore's Law curve.
"What is really needed is an absolute measure of transistors in a given area (per mm2). At the other extreme, simply taking the total transistor count of a chip and dividing by its area is not meaningful because of the large number of design decisions that can affect it—factors such as cache sizes and performance targets can cause great variations in this value. It’s time to resurrect a metric that was used in the past but fell out of favor several nodes ago. It is based on the transistor density of standard logic cells and includes weighting factors that account for typical designs," Intel said last year.
The takeaway, from Intel's perspective, is that its 10nm node isn't just notable because of the die shrink, but because of the number of transistors it was able to squish into each square millimeter, and overall. So even though AMD is already looking ahead to 7nm, Intel is essentially claiming that its process node is more impressive.
How it all plays out remains to be seen. We'll have to wait until next year when Cannon Lake finally arrives in volume, and on the desktop.