AMD 7nm Zen 2 'Rome' EPYC CPUs Reportedly Double Available L3 Cache

AMD Dr Lisa Su Epyc Rome
AMD has gone on record saying it's "betting big on 7 nanometers" and the innovations that come with it. One of its upcoming 7nm products is "Rome," a next-generation Epyc processor that will be the world's first 7nm datacenter CPU, with increased instructions per clock (IPC) throughput and a big overall performance lift. Part of that performance lift will apparently come from having twice as much L3 cache as current-generation Epyc processors.

How do we know this? AMD didn't offer up any specific details about Rome, at least not on a fine grain level. However, with a launch being imminent and with silicon already out in the wild, leaks are bound to happen.

That brings us to a database entry for SiSoft Sandra, a popular benchmarking and diagnostics utility that we ourselves use in some of our reviews. For a brief period, there was an entry for a 2P AMD Rome Epyc machine. Unfortunately the entry seems to have been deleted, but fortunately not before TechPowerUp could grab a screenshot.

AMD Epyc SiSoft Sandra
Click to Enlarge (Source: TechPowerUp via SiSoft Sandra)

The database entry shows a system with a pair of 64-core Epyc Rome processors, each made up of eight 7nm 8-core Zen 2 CPU chiplets paired to a 14nm I/O controller die, as AMD previously outlined. The controller die handles the memory and PCIe connectivity chores.

Where things get interesting is in looking at the cache allotment. The database entry shows 512KB of dedicated L2 cache per core, and 16 x 16MB of L3 cache. Note that for a Ryzen 7 2700X desktop processor, Sandra shows 2 x 8MB of L3 cache.

Since there are eight chiplets, this seems to indicate that each one features 16MB of L3 cache, with the chip's 8 cores split into quad-core CCX units containing 16MB of L3 cache apiece. If true, that effectively doubles the L3 cache per CCX, which can help with data transfers between the chiplet and I/O die.

That's assuming everything is being read and extrapolated correctly. Bear in mind that this data is coming from a third-party utility, and that the two Rome chips are engineering samples, meaning they may not be indicative of the final hardware. Typically though, there aren't major changes this late in the game.

The 64-core/128-thread Epyc processors on display here will be AMD's top-end Rome CPUs when they arrive. They're also socket-compatible with previous generation Epyc platforms, as well as the company's upcoming Milan server platform that supports PCIe 4. These chips will go up against Intel's Cascade Lake-SP CPUs shipping later this year, and Cascade Lake-AP processors shipping in early 2019.