VIA Nano DC Platform Preview Sneak Peek

During the summer of 2008, we published a number of articles detailing the design and launch of VIA’s Isaiah core, which would eventually be called the Nano. At right about the same time, Intel’s Atom processor was generating massive amounts of buzz in the mobile and entry-level desktop space, due to its low-power characteristics. But VIA quickly began shouting from the rooftops, extolling the virtues of their new low-power core, which would supposedly offer much better performance than Atom, albeit in a slightly higher power envelope. And our initial testing of Nano confirmed much of what VIA had been saying. In the performance summary of our first head-to-head comparison between Nano and Atom, we said, “In general, the VIA Nano is a stronger performer than the Intel Atom across a variety of workloads. Our test setups prohibited an exact "apples-to-apples" comparison, but the performance deltas we recorded more than make up for the clock speed discrepancy between our test systems. While the VIA Nano L2100 processor we tested had a 200MHz, or 12.5%, higher clock frequency than the 1.6GHz Atom 230, it typically outperformed the Atom by more than 15% to 20% in the applications we tested.”

Today, VIA is announcing an update to the Nano platform and is unveiling a new dual-core variant of the processor—the Nano DC—and announcing support for the VN1000 chipset that was released back in December '09, which sports a DX10.1 class integrated graphics core.

The core CPU architecture of the VIA Nano DC doesn’t differ from the original Nano; there is simply double the number of processor resources on die. To reiterate some of the design aspects of the original, the VIA Nano is a 64-bit, superscalar, speculative out-of-order processor (Atom is an in-order design). The original chips leveraged Fujitsu’s 65nm process technology and offered better power efficiency than older 90nm VIA C7 processors, which they were pin-compatible with, despite Nano having roughly twice the numbers of transistors.

Using Fulitsu’s 65nm manufacturing process, VIA Nano processors have a die size of 7.650mm x 8.275mm, or about 63 square mm, versus the 32 square mm of the 90nm-based C7. Nano processors used the same packaging, however, VIA's compact 21mm x 21mm NanoBGA2 package. The new Nano DC processors will be manufactured using TSMC’s 40nm process, and while we don’t have die size specifics as of yet, we have been told the dual core chips will have the same max 25W TDP (@1.8GHz) of the single core offerings.

VIA Nano Core Die Map

Some of the other main features of the VIA Nano include:

  • 64-bit Superscalar Speculative Out-Of-Order MicroArchitecture: Supports a full 64-bit instruction set and provides for macro-fusion and micro-fusion functionality, and sophisticated branch prediction for greater processor efficiency and performance.
  • High-Performance Computation and Media Processing: The high-speed, low power VIA V4 Front Side Bus starting at 800MHz, plus a high speed floating point unit, support for new SSE instructions, and two 64KB L1 caches and 1MB exclusive L2 cache with 16-way associativity gives a big boost to multimedia performance.
  • Advanced Power and Thermal Management: Aggressive management of active power includes support for the new “C6” power state, Adaptive PowerSaver Technology, new circuit techniques and mechanisms for managing the die temperature, reducing power draw and improving thermal management.
  • Scalable Upgrade to VIA C7 Processor: Pin-to-pin compatibility with current VIA C7 processors enables a smooth transition for OEMs and mainboard vendors, enabling them to offer a wider range of products for different markets with a single board or system design.
  • Greener Technology: In addition to full compliance with RoHS and WEEE regulations, product manufacturing will be halogen-free and lead-free at launch, helping to promote a cleaner environment and more sustainable computing.
  • Enhanced VIA PadLock Security Engine: Industry-leading on-die hardware cryptographic acceleration and security features, including dual quantum random number generators, an AES Encryption Engine, NX execute protection, and SHA-1 and SHA-256 hashing.

VIA Nano DC Processor and Architecture Diagram

Like its predecessor, the new Nano DC processor uses VIA's 800MHz V4 front side bus to interface with the core logic chipset. Note, there are no shared resources or links for inter-core communications on the CPU die. Although part of single die, the dual execution cores in the Nano DC operate like two independent processors.

VIA Nano DC and VN1000 Chipset Block Diagram

The main attraction of the VIA VN100 chipset is its integrated Chrome 520 graphics Core. The Chrom 520 is a fully programmable, 128-bit integrated DirectX 10.1 graphics core that supports shader Model 4 and OpenGL 2.0. It is outfitted with 32 stream processors and offers anti-aliasing support, along with OpenCL1.0 support for GPGPU applications. The VN1000 northbridge supports both DDR2 and DDR3 memory types, one x8 and four x1 PCIe lanes, and support for all of the major display outputs, like VGA, DVI, HDMI, and DisplayPort. The VT8261 southbrige offers a host of connectivity, as outlined in the block diagram above.


VIA Nano DC / VN1000 Test Platform

To test the new VIA Nano DC platform, we got our hands on a VT8591B reference platform, which is pictured here. Unfortunately, we ran into some technical difficulties and weren't able to run any benchmarks.  We have been in contact with VIA, however, and are hoping to have a replacement in the labs shortly. When we do, we'll run it through our full suite of tests and report back a quickly as possible.  For now, enjoy the pics.