BIOS Settings for the Athlon 64 Platform
There is a very informative article on-line today over at Lost Circuits. Mike Schuette go into great detail on HT link and bus control, memory timings, and numerous other Athlon 64 BIOS settings. Even the most experienced amongst you will learn something from this article...
"The Command Per Clock sets the Command Rate for the memory controller. At 1T, the controller can issue commands on every clock cycle, if set to 2T, the controller can issue commands only on every other bus cycle. A 2T command rate can be somewhat problematic for a number of reasons. In a first generation DDR architecture, the 2 T command rate can cause bus contention because it can mitigate the advantages of bank interleaving. For example, when using 2:2:2 latency settings, the read command would be issued 2 cycles after a bank activate command. So far so good, according to this there is apparently no need for a 1T CMD rate. However, since bank interleaving allows the opening of several pages in different banks of the same memory device, the second bank activate command that would follow immediately after the first bank activate command cannot be issued because a read command for the first bank is already scheduled. Because of this bus contention, the next possible time slot for the next bank activate command will coincide with the second read command (in case there is a page hit) and so on until there is a no-op (no operation) interval at which the bank activate command can finally be executed. Needless to say that as a result the advantages of bank interleaving are largely negated."
