AMD Demonstrates ARM-based APU, New Class Of Network Hardware

Today, at ARM TechCon, AMD is kicking off the conference by launching its new embedded ARM platform (codenamed Hierofalcon) and its associated ARM Cortex-A57 chip, codenamed Seattle. This new solution is debuting inside the first ARM-based network function virtualization platform, and is meant as a proof-of-concept demonstration that shows AMD can build enterprise networking hardware around an ARM platform and that the chip can handle data migration from an x86 platform.

Network Function Virtualization? What's That?

To understand the play AMD is making here, it helps to delve just a little into the world of big iron industrial networking. In the past, network flow control has been dominated by huge switches and extremely expensive, dedicated hardware. The complex work of traffic routing and handling primarily rested on the networking hardware itself -- but that also makes it hard (and expensive) to scale or adjust network deployments.

There have been two big pushes to address this -- Software Defined Networking (SDN) and Network Function Virtualization (NFV). Despite being sometimes positioned against each other, NFV and SDN are more complements than adversaries and attempt to address some of the same problems in different ways. In some cases, NFV and SDN can be deployed side-by-side across the same network -- the goal, in both cases, is to move the heavy lifting over to virtual machines running on commodity x86 or ARM hardware.



There's an excellent blog post by Patrick Moorhead, available here, if you want more information on NFV, SDN, and how they augment or replace traditional network infrastructure.

This is where AMD's Hierofalcon comes in. The company's press release explains it like this:
With NFV, much of the intelligence currently built into proprietary, specialized hardware is accomplished with software running on general purpose hardware. The resulting solution is a fully virtualized communications infrastructure – including virtual servers, storage and networks – and simplifies deployment and management for network and telecommunications service providers. With both 64-bit ARM and x86, AMD is paving the way for a new class of service providers to design and deploy an infrastructure which meets their performance, cost and complexity requirements.
The long-term goal is to create an AMD-centric series of solutions that offers customers an embedded x86 and ARM option for handling this kind of workload in a VM. AMD worked extensively with ARM, Aricent, and Mentor Graphics to build its demo platform and enable a Linux-on-ARM solution -- presumably it'll continue to partner with these companies to offer commercial software going forward. Hierofalcon isn't shipping quite yet, but AMD has reiterated that the platform will include up to eight Cortex-A57 chips running at up to 2GHz with a 15-30W TDP, 10Gb KR Ethernet, PCI Express 3.0, and two 64-bit DDR3 or DDR4 memory channels with support for ECC RAM. An embedded Cortex-A5 for security applications is also included. 

Via:  AMD
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