10-Petaflop Supercomputer To Use Intel’s MIC Architecture

Geez, didn’t supercomputing just break the petaflop barrier a few years ago? Already, the Texas Advanced Computing Center (TACC) and the University of Texas at Austin announced a supercomputer that will be capable of 10 petaflops. Dubbed “Stampede” (we see what you did there, University of Texas Longhorns), the beast will be completed in early 2013.

Intel touted this announcement in a blog post today, and the company is understandably pleased with itself, as Stampede’s processing power will be an all-Intel affair. Of those 10 petaflops, two will be delivered by Intel’s 8-core Xeon E5 processors. The other eight will be provided by Intel’s forthcoming Many Integrated Core (MIC) co-processors.

Although Intel expects the Xeon E5s to power plenty of supercomputers (as well as a variety of other applications from workstations to cloud computing), it’s understandably pumped about the use of its MIC architecture.

First announced last spring at the International Supercomputing Conference (ISC), processors built on the MIC architecture will be designed specifically for HPC purposes and other applications that require highly parallel processing. Intel’s R&D teams have been working toward this end for a while now; the work done on the 80-core Tera-scale research chip, single-chip cloud computing, and Larrabee many-core visual computing projects all contributed to the creation of MIC.

In the blog post, Intel offers the following description of the MIC architecture:

“The architecture utilizes a high degree of parallelism in smaller, lower power, and single threaded performance Intel processor cores, to deliver higher performance on highly parallel applications. While relatively few specialized applications today are highly parallel, these applications address a wide range of important problems ranging from climate change simulations, to genetic analysis, investment portfolio risk management, or the search for new sources of energy.”

The MIC architecture puts a number of cores on a single chip, and those cores are programmable with the same tools and code as Xeon processors, which is a feature designed to help researchers get right to it, as it were, rather than getting bogged down in learning new programming models.

The first MIC co-processor to hit the commercial market, and the one slated for use in Stampede, is codenamed “Knights Corner”. Built on Intel’s 22nm 3D Tri-Gate transistor technology, Knights Corner will feature over 50 cores.

Over time, TACC is planning to increase Stampede’s peak performance to 15 petaflops with future MIC-based co-processors.

In addition to Intel’s contributions, Stampede will have thousands of Dell Zeus servers (comprising 14PB), run NVIDIA graphics, utilize a Lustre file system, and feature an InfiniBand FDR 56Gb/s network.

It’s impressive how far supercomputing has come in a remarkably short time. Next stop: Exaflop?