AMD Spider Platform - Phenom, 790FX, RV670

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At the heart of AMD's Spider platform is the native quad-core Phenom processor.  Phenom is the brand name given to processors based on the Agena core, which is virtually identical to the Barcelona core used in the recently released AMD quad-core Opterons.
 

      


In a quad-core Phenom processor, each of the four cores is outfitted with 64K of L1 instruction and 64K of L1 data cache, for a total of 512K of L1 cache per CPU.  The L2 cache compliment of each core is 512K, for a total of 2MB.  New to the Barcelona and Agena cores is 2MB of dynamically shared L3 cache.   Unlike L1 and L2 caches, which are exclusive to each execution core (data in Core 1’s L2 cache cannot be accessed by Core 3, for example), the L3 cache is shared among all the cores.  Also new to Barcelona and Agena is a 128-bit wide memory controller that can be configured as dual independent 64-bit channels to allow for simultaneous read and write memory operations.

Currently, all Phenom processors will be built in AMD’s Dresden, Germany facility using the company’s 65nm SOI (silicon on insulator) manufacturing process.  Each quad-core die is comprised of approximately 463M transistors (about 357M less than Intel’s quad-core Yorkfield) and is about 285mm2 in size.
 

      



Looking deeper into the Phenom's native quad-core, single die architecture, we've learn that the cores themselves have been revamped considerably for efficiency and performance. Here are a few of the key salient points of Phenom's new core micro-engines:

 

  • A new floating point scheduler now supports 36 128-bit operations
  • Support for 128-bit SSE operations, an upgrade from the previous 64-bit architecture
  • Two SSE operations and one SSE move can be processed per cycle
  • Processor instruction fetch has been increased from 16 to 32 bytes
  • Advanced branch prediction with built in a 512-entry indirect branch predictor
  • Data cache bandwidth has increased from 1 x 64-bit loads per cycle to 1 x 128-bit loads per cycle
  • L2 cache / memory controller bandwidth has been increased from 64-bits per clock to 128-bits per clock
  • HyperTransport 3.0 Support for up to 20.8GB/s of raw bandwidth


In addition to the enhancements listed above, Phenom processors support dynamic clock gating on a per-core basis.  Though core voltages won't be managed independently, the clock speed of each core can throttle back when idle, which could in turn provide significant power savings. And AMD's "CoolCore" technology allows for functional blocks of each core to be shut off when not in use, further improving power efficiency.  You may have heard of AMD's "Dual Dynamic Power Management" technology referred to as "split power planes" in the past.

We should note that to fully take advantage of AMD's "Dual Dynamic Power Management" technology, a next-gen platform must be used.  Users that drop a Phenom into an existing socket AM2 platform will not have support for split power planes, because current motherboards lack the necessary support.

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Good review, thank you. AMD needs to get more IPC though. Or something. We went the frequency to stay as low as possible to help power usage. I guess for this core design, all we can hope for is them to ramp up the frequency.... and hope that the next core can get massively better number at lower clocks. Other than buying one, I wish there was some way I could help them. I don't know anything about chip design and I'm pretty bad at math, so I'd be no use. But if I could help, I would.

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This one is easy, at least from my perspective. AMD needs to simply incorporate larger on-chip cache. They're currently in 65nm versus Intel's 45nm, so incorporating on-die cache is more expensive, die real estate-wise for AMD than it is for Intel. BUT that's the one true way to increase IPC efficiency and I'm fairly certain it's largely why Intel is faster clock for clock.

With smaller L2 cache, AMD has to go "off chip" for data more often than Intel's architecture does. This was a necessity for Intel, since their FSB arch limits their available bandwidth going off chip versus HyperTransport for AMD which has a lot more bandwidth. However, regardless, if you have to go off chip to process, rather than stuffing a bunch more in cache and then just pipelining, it's going to cost you performance.

If AMD had 8 to 12MB of on-chip L2, things might look decidedly different but that would cost a bit in power and heat as well, especially at 65nm, which is another story all together and something that AMD is obviously dealing with as well.

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i got to agree good review 

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Hundred percent agree, stuff a load of cache on chip, crank up the 45nm process time frame, and maybe stand a chance with performance against Intel.  I think partially it's in doing so they'll increase the cost and so lose their one solid edge against Intel.  If they weren't cheaper right now who'd buy. 

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The AMDs are not worth it at all, not only they perform poorly compared to the Intel Quad-Cores, but also use more power than the most powerful Intel Processor now. Excellent Review by the way. :)

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Progress is progress, however meager it may be. It would be nice if AMD were more of a threat to Intel, rather than always one step behind. Hopefully they will be able to shorten the gap with their 45nm chips, but by the time they get them out Intel may verywell be onto bigger (or smaller) and better things.

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AjayD:

Progress is progress, however meager it may be. It would be nice if AMD were more of a threat to Intel, rather than always one step behind. Hopefully they will be able to shorten the gap with their 45nm chips, but by the time they get them out Intel may verywell be onto bigger (or smaller) and better things.

 

And that is indeed happening, Nehalem will slap Shanghai right out the door...I'm predicting it now...so in 7-9 months from now..I'll be the first to say I tell everyone I told you so Stick out tongue.

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