AMD is keeping some of the intricate details of their latest Fusion APU architecture close to the vest, but below is a relatively detailed block diagram of what you get with the A8 processor that we'll have benchmarks numbers for you on, later in this article.
The A8 consists of four AMD Phenom-class cores with 128-bit FPUs. Each core has its own 1MB L2 cache and the chip now supports low power C6 idle states, as well as CC6 power gating, allowing individual cores to power down completely. More on this later. Also on board is a DX11 capable GPU; you can see how large the graphics array is, as well as its companion Display output and UVD3 (Unified Video Decoder) blocks. Finally, on chip also resides a dual channel DDR3 memory controller supporting speeds up to 1600MHz (though our system came configured at 1333MHz), as well as a X16 PCI Express link and four X1 PCI Express links.
Llano Bus and Interconnect Block Diagram
Here AMD illustrates the various interfaces employed between each sub-block of the A-Series APU architecture. Since we're already familiar with the DDR memory and CPU bus interfaces employed in the CPU block, of particular interest are the two new interfaces, known as the "Radeon Memory Bus" and "Fusion Compute Link." The FCL is a bit misleading in its terminology, however. With the word "link" in there, you might confuse it for a serial connection (commonly referred to as links) but it is in fact a parallel bus interface, believe it or not. Here's what AMD had to tell us about it: "The Fusion Controller link is similar to the HT interface used to communicate to our Integrated Graphics Chips, but with the Physical layer stripped off. As such it uses an HT like protocol, but is implemented as a wide parallel bus interface." Interesting. It can't really be a "bus" though can it? When we think of bus architectures we think of things like arbitration and latency but that would be on a "shared" bus architecture. This is a dedicated connection. Regardless, this is all the information AMD was willing to share with us at the moment on FCL.
The Radeon Memory bus is a bit easier to wrap your head around. Here's what AMD had to offer on it: "The Radeon Memory bus aggregates requests from all the Graphics and Multimedia clients and presents a well-ordered (for DRAM efficiency) stream of requests to the back end of the NorthBridge. These requests bypass any of the coherency mechanisms associated with the front-end of the Northbridge. The Radeon Memory bus is capable of making all the system memory bandwidth available to the Radeon compute Units." Ahh, an intelligent DMA Engine and interface that essentially circumvents the Northbridge memory manager. Got it.
In addition to improved IPC (instructions per clock) throughput for each of the four CPU cores, AMD has enabled Llano with their Turbo Core technology, allowing the processor to scale up frequency on a per-core basis depending on workload, or ramp down and completely power off cores that are not in use. Again, this can happen on a per-core basis at the CPU level and gating of the GPU and UVD blocks is available as well. AMD even developed a method of optimizing display power by balancing backlight and pixel brightness to provide an optimal image while reducing power consumption. In the bottom right image above here, you can see the results of the Graphics and UVD blocks in a gated state. In this state, the only power consumption is due to intrinsic leakage current in the circuit areas but all clocks are off. In the thermal images above, blue areas represent how cool the powered-down blocks are, reaching ambient air temp.
AMD "Sabine" Platform with Optional Vancouver Discrete Graphics
Finally, a quick look at the full system implementation here, shows a base two-chip solution that employs AMD's new Fusion Controller Hub Southbridge. Specifically, the A70M version of the FCH is what enables USB 3.0 connectivity, though both the A60M and A70M support 6Gbps 3G SATA connectivity as well. As you can see, Llano itself supports 2 DDR3 DIMM sockets, as well as DP and HDMI outputs and a X16 PEG (PCI Express Graphics) link to an optional discrete GPU. This is how our system was setup, with an additional Radeon HD 6630M series chip on board. Incidentally, AMD enables CrossFire rendering with Llano's IGP, for discrete GPUs in tandem, allowing for higher performance.