|Introduction and Penryn Details|
Intel held a briefing today to further disclose and discuss details regarding their upcoming 45nm High-K Penryn and Nehalem processor cores. Roughly two years ago, Intel talked about their proposed "tick-tock" product strategy which entailed the shift to a new process technology followed by an enhanced or entirely new microarchitecture approximately every year.
Today we have more details regarding 2007's "tick", the Penryn core, and next year's "tock", the Nehalem core, which also ushers in significant changes to Intel's platform architecture as a whole.
As we mentioned in our coverage of their 45nm High-K and metal gate transistor re-announcement in January, Penryn is the lead vehicle for Intel's 45nm manufacturing process. Penryn will offer a number of enhancements over current Conroe and Kentsfield-base Core 2 processors.
Penryn will be the first core to benefit from the 45nm High-K and metal gate transistor technology and will be the foundation of future processors that span each product segment (mobile, desktop, and server) and power envelope. Penryn, however, is not just a die shrink of Conroe. Penryn is built upon and enhanced Core microarchitecture designed to offer greater performance at a given frequency, while at the same time operating at even higher frequencies. Penryn also ushers in new SSE4 instructions for Media / Gaming / Graphics developers, new levels of Energy Efficiency, improved Virtualization performance, larger caches, and faster Buses.
Today Intel disclosed that Penryn will feature a 4-bit per cycle divider, that the company claims will offer 4X the performance of current processors for square root operations and increased performance computing transcendental. Intel has dubbed this new feature their Fast Radix-16 Divider. In addition to this, Penryn will also feature new Deep Power Down Technology. Deep Power Down Technology ia essentially a new CPU power state that turns off the clocks and caches and significantly lowers voltage while idle. With Deep Power Down Technology in addition to the benefits inherent to 45nm High-K and metal gate transistors, Penryn should offer huge improvements in idle leakage power consumption. Intel did point out that it does take longer for the CPU to get into and out of the Deep Power Down state versus other C states, however.
Another new feature incorporated into Penryn is called Enhanced Intel Dynamic Acceleration Technology. This feature allows one core within the processor to take advantage of the power budget of a second core, when that second core is not being fully utilized. This feature is designed to enhance the performance of single-threaded workloads. Enhanced Intel Dynamic Acceleration Technology is basically dynamic optimization of the power budget, which enhances the efficiency of the processor with certain workloads.
Along with the architectural details, Intel also shared some preliminary performance data regarding Penryn. In the mobile and desktop arenas, a Penryn derivative running at 3.2GHz offered performance roughly 20% higher than today's most powerful Merom or Conroe-based systems while running existing software.
Taking Penryn's higher clocks into consideration as well, SSE4 should offer performance enhancements to media codecs that take advantage of the technology of greater than 40%. This is accomplished through new instructions and a new Super Shuffle Engine that improves performance for SSE2, SSE3 and SSE4 instructions that have shuffle-like operations such as pack, unpack and wider packed shifts.
And in servers Intel is saying >45% performance improvements are possible in situations that are bandwidth and floating point intensive. We should point out that these improvements represent the performance deltas between the fastest Penryn derivatives versus the fastest processors of today. In the server space, the comparison was made between a 2.67GHz Clovertown CPU and a >3GHz Penryn riding on a 1600MHz FSB. An interesting side note to this performance data is that Intel ran the entire presentation on a 3.33GHz Penryn with a 1333MHz FSB, to further demonstrate the technology is working and on schedule for production this year. Penryn will appear in server space first, followed by the desktop and mobile spaces.
|Nehalem Details and Conclusion|
After Penryn and the 45nm High-K silicon technology introduction comes Intel's next-generation microarchitecture, dubbed Nehalem, which is slated for initial production in 2008. With Nehalem Intel plans to deliver further performance and energy efficiency gains, and more performance-related features and capabilities for new and improved applications.
Below is a list of the new initial disclosures Intel has made regarding the Nehalem microarchitecture:
According to Intel, Nehalem is the company's first truly dynamically scalable microarchitecture and Intel considers the Nehalem system and interconnect architectures the biggest system architecture transition since the introduction of the FSB.
Nehalem is a new microarchitecture that leverages much of the technology introduced with the Conroe. With Nehalem, however, each processor core is capable of executing two threads simultaneously, similar to the way Hyper-Threaded worked. Nehalem also features a multi-level shared cache architecture, with the last level of cache being shared, which balances on-die resource across multiple threads.
Nehalem is also natively architected to take full advantage of 45nm, and with Nehalem will come a totally new system architecture and a next-gen platform architecture. There will be different sockets across different market segments with configurations capable of handling 1 - 16+ threads (8 Cores) and 1 - 8+ cores (16 threads).
Perhaps in its biggest departure from current products, Nehalem will feature a new link-based architecture, with some configurations sporting integrated DDR3 memory controllers, and integrated graphics for some market segments. Intel was unclear how the memory controllers and integrated graphics would be configured, but it was said that the graphics core will reside in the processor socket, not necessarily on the same die though. Intel did not disclose how many links would be part of the architecture, core configurations, etc. They simply wanted to describe some of the possibilities of the new platform and system architectures.
According to Intel, Nehalem is on track for '08 and designs featuring 8 cores are already underway.