Intel Announces MIC Xeon Phi For Exascale Computing

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At the International Supercomputing Conference today, Intel announced that Knights corner, the company's first commercial Many Integrated Core (MIC) product will ship commercially in 2012. The Descendent of the processor formerly known as Larrabee also gets a new brand name -- Xeon Phi.





The idea behind Intel's new push is that the highly efficient Xeon E5 architecture (eight-core Sandy Bridge on 32nm) fuels the basic x86 cluster, while the Many Integrated Core CPUs that grew out of the failed Larrabee GPU offer unparalleled performance scaling and break new ground.

The challenges Intel is trying to surmount are considerable. We've successfully pushed from teraflops to petaflops, but exaflops (or exascale computing) currently demands more processors and power than it's feasible to provide in the next 5-7 years. MIC is meant to hammer away at that barrier and create new opportunities for supercomputing deployments.




Along with the brand name come some additional details. The Xeon Phi alone will deliver an estimated 800GFlops of double-precision floating point performance (the total figure of 1TFlop includes the two Xeon E5 processors in the system). The chip's 50 cores are fed by at least 8GB of onboard RAM; Intel hasn't yet announced if there will be multiple SKUs with different RAM counts. Nvidia's previous top-end Tesla board, the M2090, topped out at 665 GFlops of double-precision performance and 6GB of RAM. Team Green's recently announced K10 GPU, based on Kepler, offers 8GB of RAM but tops out at an anemic 190GFlops of double-precision floating point.
 

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