Intel 45nm Fab Process And Penryn Preview
Intel's impressive manufacturing process capabilities and fab resources are well known throughout the industry. In fact, most would argue that their manufacturing prowess has played a large part in the company's success. They've had many "firsts" over the years due to process advancements, the most recent of which was their successful cross-over from 90nm to 65nm mass production. Due to that success Intel has already shipped millions of processors manufactured at 65nm.
Today, Intel is announcing a breakthrough that will affect future products scheduled to be manufactured using the company's even more advanced 45nm process. A major issue that become more significant as manufacturing processes get smaller is current leakage. Leakage occurs through multiple parts of a semiconductor, but one of the most problematic situations occurs when unwanted current flows through the gate dielectric in a transistor. Ideally, the gate dielectric would act as a perfect insulator. But because it is made ever thinner as manufacturing processes advance and die geometries continue to shrink, current leaks through gate dielectric. In Intel's 65nm process, it is only 5 atomic layers thick. This leads to undesirable results and the transistor consumes more power than it should.
With their 45nm process, however, Intel has been able to develop and successfully implement a high-k (capacitance) and metal gate transistor that significantly reduce leakage current. According to Intel, the combination of manufacturing processors using their 45nm process, in conjunction with the high-k and metal gate transistor breakthrough will offer a number of key benefits:
- ~2x improvement in transistor density, for either smaller chip size or increased transistor count
- ~30% reduction in transistor switching power
- >20%improvement in transistor switching speed or >5x reduction in source-drain leakage power
- >10x reduction in gate oxide leakage power
In the image above, a traditional polysilicon gate MOS transistor is on the left and one of Intel's new high-k and metal gate transistors is on the right. These structures differ in two key ways. First, the polysilicon gate in the standard transistor has been replaced with a metal gate. What metals are being used exactly have not been disclosed, but Intel did say that the metals being used for NMOS and PMOS transistors are different. The second difference between the two is that the polysilicon gate of the standard transistor has been replaced with a Halfnium-based High-K gate oxide.
The advantages of the high-k and metal gate transistor are outlined in the image above (the red arrows indicate area of current leakage). The high capacitance metal gate and high-k dielectric both work together to increase the gate field effect. And the use of a thicker dielectric layer reduces gate leakage. When combined, the drive current can be increased by over 20%, which in turn improves performance by a similar amount. And source-drain leakage (the arrow running left to right) and gate oxide leakage (the arrow running up and down) are both reduced by factors of 5 and 10, respectively.
Above we have a high-power micrograph of one of Intel's high-k and metal gate transistors. This is one of the actual transistors found in one of Intel's upcoming processors manufactured at 45nm, and not a lab device. The image shows the different layers that make up the actual transistor. If you look close you can actually see the individual atomic layers in the silicon substrate at the bottom.
Intel is able to build these new transistor using mostly existing tools, but the high-k material is deposited by new processing step, dubbed atomic layer deposition. Deposited materials are laid down one atomic layer at a time with very precise control.