"For years we have seen limits to how small transistors can get," said Gordon E. Moore. "This change in the basic structure is a truly revolutionary approach, and one that should allow Moore's Law, and the historic pace of innovation, to continue."
What Intel has done is adopt a 3D gate structure that creates a fin of substrate material through which the gate passes. This actually increases the size of the inversion layer (allowing for higher drive current) but minimizes the power lost to leakage. Intel's diagrams indicate that the company is moving to SOI as well.
The image on the left is a model of fully-depleted SOI--a manufacturing method championed by AMD and IBM, and one that Intel states raises chip costs by about 10 percent. The right-hand model is Intel's own fin approach. The color and labeling of the light blue blocks implies that while Intel isn't using SOI the same way AMD is, it's still deploying it at 22nm.
"Intel's scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension. Amazing, world-shaping devices will be created from this capability as we advance Moore’s Law into new realms.", said Paul Otellini, Intel President and CEO.
We've linked to Intel's explanations and discussions below. The takeaway here is that building chips in this way will allow Intel to ramp transistor density, cut power usage, and (potentially) increase clockspeeds. Don't expect the company to unilaterally leap one way or the other; the technology is complex enough that Intel can use it to improve various products in a number of ways.
"The performance gains and power savings of Intel's unique 3-D Tri-Gate transistors are like nothing we've seen before. This milestone is going further than simply keeping up with Moore's Law. The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next. It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel's lead even further over the rest of the semiconductor industry.", said Mark Bohr, Intel Senior Fellow
Planar Transistor Structure (left) 3D Tri-Gate Transistor Structure (right)
The 3D images above depict conventional planar transistor technology and Intel's new Tri-Gate transistor structure. On the left, a planar gate is resting on a standard silicon substrate (the gate oxide is the bright yellow line). On the right, the substrate 'fin' pokes upwards and the gate wraps around it. The gate oxide / inversion layer actually makes better contact here, which gives Intel more control over drive strength.
32nm Planar Transistor (left) 22nm 3D Tri-Gate Transistor (right), Similar Magnification
The fins and their connectors are easily visible in the image to the right here, which shows an actual Tri-Gate transistor, heavily magnified. We're now hungry for waffle fries.
To coincide with the announcement, Intel has also released a number of videos that explain the ew Tri-Gate transistor technology. Intel's explanation of 22nm and gate lengths is posted above.
The next two videos break out the transistor design in more detail and highlight Intel's demonstration of the first Ivy Bridge products. Above, Senior Analyst for VLSI Research, Dan Hutcheson, talks about the fundamental changes to Intel's transistor design and below are a couple of demos of actual products based on working silicon.
Intel has stated that all of the transistors manufactured on the upcoming 22nm processes will use the Tri-Gate design. The full text of Intel's press release outlining the technology is shown below.
New Transistors for 22 Nanometer Chips Have an Unprecedented Combination of Power Savings and Performance Gains
SANTA CLARA, Calif., May 4, 2011 – Intel Corporation today announced a significant breakthrough in the evolution of the transistor, the microscopic building block of modern electronics. For the first time since the invention of silicon transistors over 50 years ago, transistors using a three-dimensional structure will be put into high-volume manufacturing. Intel will introduce a revolutionary 3-D transistor design called Tri-Gate, first disclosed by Intel in 2002, into high-volume manufacturing at the 22-nanometer (nm) node in an Intel chip codenamed "Ivy Bridge." A nanometer is one-billionth of a meter.
The three-dimensional Tri-Gate transistors represent a fundamental departure from the two-dimensional planar transistor structure that has powered not only all computers, mobile phones and consumer electronics to-date, but also the electronic controls within cars, spacecraft, household appliances, medical devices and virtually thousands of other everyday devices for decades.
"Intel's scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension," said Intel President and CEO Paul Otellini. "Amazing, world-shaping devices will be created from this capability as we advance Moore's Law into new realms."
Scientists have long recognized the benefits of a 3-D structure for sustaining the pace of Moore's Law as device dimensions become so small that physical laws become barriers to advancement. The key to today's breakthrough is Intel's ability to deploy its novel 3-D Tri-Gate transistor design into high-volume manufacturing, ushering in the next era of Moore's Law and opening the door to a new generation of innovations across a broad spectrum of devices.
Moore's Law is a forecast for the pace of silicon technology development that states that roughly every 2 years transistor density will double, while increasing functionality and performance and decreasing costs. It has become the basic business model for the semiconductor industry for more than 40 years.
Unprecedented Power Savings and Performance Gains
Intel's 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency compared to previous state-of-the-art transistors. The capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application.
The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel's 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to "switch" back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.
"The performance gains and power savings of Intel's unique 3-D Tri-Gate transistors are like nothing we've seen before," said Mark Bohr, Intel Senior Fellow. "This milestone is going further than simply keeping up with Moore's Law. The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next. It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel's lead even further over the rest of the semiconductor industry."
Continuing the Pace of Innovation – Moore's Law
Transistors continue to get smaller, cheaper and more energy efficient in accordance with Moore's Law – named for Intel co-founder Gordon Moore. Because of this, Intel has been able to innovate and integrate, adding more features and computing cores to each chip, increasing performance, and decreasing manufacturing cost per transistor.
Sustaining the progress of Moore's Law becomes even more complex with the 22nm generation. Anticipating this, Intel research scientists in 2002 invented what they called a Tri-Gate transistor, named for the three sides of the gate. Today's announcement follows further years of development in Intel's highly coordinated research-development-manufacturing pipeline, and marks the implementation of this work for high-volume manufacturing.
The 3-D Tri-Gate transistors are a reinvention of the transistor. The traditional "flat" two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top -- rather than just one on top, as is the case with the 2-D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the "on" state (for performance), and as close to zero as possible when it is in the "off" state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).
Just as skyscrapers let urban planners optimize available space by building upward, Intel's 3-D Tri-Gate transistor structure provides a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore's Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.
"For years we have seen limits to how small transistors can get," said Moore. "This change in the basic structure is a truly revolutionary approach, and one that should allow Moore's Law, and the historic pace of innovation, to continue."
World's First Demonstration of 22nm 3-D Tri-Gate Transistors
The 3-D Tri-Gate transistor will be implemented in the company's upcoming manufacturing process, called the 22nm node, in reference to the size of individual transistor features. More than 6 million 22nm Tri-Gate transistors could fit in the period at the end of this sentence.
Today, Intel demonstrated the world's first 22nm microprocessor, codenamed "Ivy Bridge," working in a laptop, server and desktop computer. Ivy Bridge-based Intel Core family processors will be the first high-volume chips to use 3-D Tri-Gate transistors. Ivy Bridge is slated for high-volume production readiness by the end of this year.
This silicon technology breakthrough will also aid in the delivery of more highly integrated Intel Atom processor-based products that scale the performance, functionality and software compatibility of Intel architecture while meeting the overall power, cost and size requirements for a range of market segment needs.
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