FSB Issues with Future Intel CPU's

The Inquirer is reporting that Intel is facing some major issues regarding FSB speeds with their upcoming processor architectures. Apparently, there are some major bandwidth considerations which must be made as multiple cores will all be fighting for real estate to dump data. Could Intel be forced to look beyond the traditional FSB and use another interconnect such as HyperTransport 3.0?

Outside one tech session here, a source mentioned that 1,600 FSB is the practical limit for the highly tuned point-to-point FSB on 2006 Conroe and Woodcrest, even after overclocking, assuming reliable long-term operation. With some tweaking, the whisper says that 1,333 FSB (and not a hertz more) could be done for a three-load situation like the one on Kentsfield or Clovertown, but it may take some time to fix & validate on both CPU and north bridge sides - maybe requiring that Christmas++ arrival date for these CPUs?

4/13 - 3:30PM - Editor commentary

Folks, yours truly, Dave checking in here with some random thoughts regarding this interesting news bullet Sean loaded up.  I've seen this coming for Intel for a long time now actually and it would not be surprising in the least that serial I/O is going to find its way in to Intel's core CPU arch sooner than later. I think it's probably more along the lines of a trajectory around the time Gen2 PCI Express SerDes IO technology becomes available in silicon though.  A 5Gig X8 PCI Express interface would offer plenty of bandwidth, 8GB (4 bi-directional) to be exact. Unfortunately that may not be until around Q1/Q2 '07... or so we've heard.

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