The Inquirer is reporting that Intel is facing some major issues regarding FSB speeds with their upcoming processor architectures. Apparently, there are some major bandwidth considerations which must be made as multiple cores will all be fighting for real estate to dump data. Could Intel be forced to look beyond the traditional FSB and use another interconnect such as HyperTransport 3.0?
4/13 - 3:30PM - Editor commentary
Folks, yours truly, Dave checking in here with some random thoughts regarding this interesting news bullet Sean loaded up. I've seen this coming for Intel for a long time now actually and it would not be surprising in the least that serial I/O is going to find its way in to Intel's core CPU arch sooner than later. I think it's probably more along the lines of a trajectory around the time Gen2 PCI Express SerDes IO technology becomes available in silicon though. A 5Gig X8 PCI Express interface would offer plenty of bandwidth, 8GB (4 bi-directional) to be exact. Unfortunately that may not be until around Q1/Q2 '07... or so we've heard.
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